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<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Hi Jonathan,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">Thank you very much for the tip.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">I did overwrite the translation table with an additional entry and can now successfully access the device.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US">Cheers,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="mso-fareast-language:EN-US"> Jan<o:p></o:p></span></p>
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<p class="MsoNormal"><b>From:</b> Jonathan Brandmeyer <jbrandmeyer@planetiq.com> <br>
<b>Sent:</b> Wednesday, November 18, 2020 5:01 PM<br>
<b>To:</b> Sommer, Jan <Jan.Sommer@dlr.de><br>
<b>Cc:</b> RTEMS <users@rtems.org><br>
<b>Subject:</b> Re: Acessing PL devices of Xilinx Zedboard<o:p></o:p></p>
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<p class="MsoNormal">On Wed, Nov 18, 2020 at 8:37 AM <<a href="mailto:Jan.Sommer@dlr.de">Jan.Sommer@dlr.de</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Hello,<br>
<br>
We try to use the xilinx_zynq_zedboard BSP with some devices synthesized to the PL, e.g. a Xilinx NS16550 Uart.<br>
If I try to access any of the AXI registers, I get a fatal error with a vector number 0x04 (undefined instruction).<br>
Accessing the same register address from within a Xilinx standalone hello-world program works as expected.<br>
Could it be that during the RTEMS startup some of the system initialization is reset so that accessing the PL devices fails?<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">The default memory map does not provide access to any of the PL address range. You'll have to override the weak symbol zynq_setup_mmu_and_cache to provide your own memory map. The MMU code only supports 1 MB superpages at this time.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Caveat: My information could be a little out of date. We're still running on a pre-release version of RTEMS 5.0. But hopefully this points you in the right direction. In particular, I know that some work has been done to support 4kB
pages, but I don't know if the entry point arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache currently uses that support or not.<o:p></o:p></p>
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<p class="MsoNormal"><br>
-- <o:p></o:p></p>
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<p class="MsoNormal">Jonathan Brandmeyer<br>
PlanetiQ<o:p></o:p></p>
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