<div dir="auto"><div><br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Aug 25, 2022, 12:08 AM <<a href="mailto:Padmarao.Begari@microchip.com">Padmarao.Begari@microchip.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Hesham,<br>
<br>
The generic RISC-V BSP is working on the PolarFire SoC without SMP but<br>
doesn't work with SMP because it expects first HARTID should be '0', t<br>
he PolarFire SoC SMP starts with HARTID '1'(U54) because the HARTID<br>
'0'(E51) reserved for first state booatloader. When the RTEMS is executing on the PolarFire SoC it reads hartid number with "HARTID-1" so that the SMP can start from hartid '0'.<br>
<br>
i.e reason I have added seperate BSP for the PolarFire SoC.<br>
<br>
Yes, there is a lot of code duplication and will try to re-use the<br>
existing code for the PolarFire SoC with modification.<br></blockquote></div></div><div dir="auto"><br></div><div dir="auto">You are on a path to create a BSP variant. Share entire files via build system. Set conditional variables for small things. For larger things just pick different files.</div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Will remove platform-dependent #ifdefs in startup code, is it Ok to<br>
add CPU dependent #ifdefs? </blockquote></div></div><div dir="auto"><br></div><div dir="auto">Where? Usually if they are small sections of code, it's ok in a BSP</div><div dir="auto"><br></div><div dir="auto">Just balance amount shared versus just swapping the file, refactoring a helper method which can be swapped at the file level, etc</div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <br>
<br>
Regards<br>
Padmarao<br>
<br>
On Wed, 2022-08-24 at 11:00 +0100, Hesham Almatary wrote:<br>
> Hello Padmarao,<br>
> <br>
> It would be great to have support for running RTEMS on PolarFire.<br>
> <br>
> I had a quick look at the code. There is a lot of code duplications<br>
> already. The generic RISC-V BSP already has SMP, CLINT, PLIC, and<br>
> 16550 support. Why can't this code be shared (i.e., if you use the<br>
> riscv/riscv BSP and just provide your FDT)?<br>
> <br>
> I'd also try to avoid introducing platform-dependent #ifdefs in<br>
> shared<br>
> code (e.g., start.S).<br>
> <br>
> Cheers,<br>
> Hesham<br>
> <br>
> On Wed, 24 Aug 2022 at 08:14, <<a href="mailto:Padmarao.Begari@microchip.com" target="_blank" rel="noreferrer">Padmarao.Begari@microchip.com</a>> wrote:<br>
> > Hi,<br>
> > <br>
> > I want to add a new BSP for RISC-V-based Microchip PolarFire<br>
> > SoC(MPFS)<br>
> > to RTEMS.<br>
> > <br>
> > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and a 64-bit<br>
> > RISC-<br>
> > V<br>
> > E51 monitor core SoC from Microchip.<br>
> > <br>
> > The new BSP is added for the U54 cores not for E51 because the E51<br>
> > moniter core is resreved for first stage bootloader (Hart Software<br>
> > Services).<br>
> > <br>
> > This BSP supports below components:<br>
> > <br>
> > 4 CPU Cores (U54)<br>
> > Interrupt controller (PLIC)<br>
> > Timer (CLINT)<br>
> > UART (mmuart, 16550-compatible)<br>
> > <br>
> > We have already done some work on this and tested but not with<br>
> > latest<br>
> > RTEMS source(8th March, 2022 commit) and want to send patches with<br>
> > latest source.<br>
> > <br>
> > <a href="https://github.com/polarfire-soc/rtems/tree/mpfs-rtems" rel="noreferrer noreferrer" target="_blank">https://github.com/polarfire-soc/rtems/tree/mpfs-rtems</a><br>
> > <br>
> > Regards<br>
> > Padmarao<br>
> > _______________________________________________<br>
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