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<div>On Mon, 2022-08-29 at 16:18 -0500, Joel Sherrill wrote:</div>
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<div dir="ltr" class="gmail_attr">On Fri, Aug 26, 2022 at 6:37 AM <<a href="mailto:Padmarao.Begari@microchip.com">Padmarao.Begari@microchip.com</a>> wrote:<br>
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Hi Hesham,<br>
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The boot HARTID configurable is Ok but I am thinking about SMP.<br>
<br>
The PolarFire SoC has 4 U54's with hartid 1,2,3,4 but the SMP<br>
starts with cpu number '0' to MAX cpu number then the PolarFire<br>
SoC U54's hartid number should become 0,1,2,3 to run the SMP.<br>
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<div>Yeah. I think the BSP is going to be responsible for mapping things</div>
<div>so RTEMS can ask for 0..n-1 but the BSP interacts with 1..n. If that</div>
<div>can be done via changing the base number to 0 without messing </div>
<div>anything up, that would be the simplest I think.</div>
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<div>Hi Joel,</div>
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<div>Thank you, trying to implement same with the boot HARTID.</div>
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<div>Regards</div>
<div>Padmarao</div>
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<div>--joel</div>
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Regards<br>
Padmarao<br>
<br>
On Thu, 2022-08-25 at 10:05 +0100, Hesham Almatary wrote:<br>
> <br>
> Hello Padmarao,<br>
> <br>
> I wonder if we can make the boot HARTID configuragle in RTEMS for<br>
> RISC-V. Something like introducing a new option (e.g.,<br>
> optboothartid.yml) in the generic RISC-V BSP.<br>
> <br>
> On Thu, 25 Aug 2022 at 06:08, <<a href="mailto:Padmarao.Begari@microchip.com" target="_blank">Padmarao.Begari@microchip.com</a>> wrote:<br>
> > Hi Hesham,<br>
> > <br>
> > The generic RISC-V BSP is working on the PolarFire SoC without SMP<br>
> > but<br>
> > doesn't work with SMP because it expects first HARTID should be<br>
> > '0', t<br>
> > he PolarFire SoC SMP starts with HARTID '1'(U54) because the HARTID<br>
> > '0'(E51) reserved for first state booatloader. When the RTEMS is<br>
> > executing on the PolarFire SoC it reads hartid number with "HARTID-<br>
> > 1" so that the SMP can start from hartid '0'.<br>
> > <br>
> > i.e reason I have added seperate BSP for the PolarFire SoC.<br>
> > <br>
> > Yes, there is a lot of code duplication and will try to re-use the<br>
> > existing code for the PolarFire SoC with modification.<br>
> > <br>
> > Will remove platform-dependent #ifdefs in startup code, is it Ok to<br>
> > add CPU dependent #ifdefs?<br>
> > <br>
> > Regards<br>
> > Padmarao<br>
> > <br>
> > On Wed, 2022-08-24 at 11:00 +0100, Hesham Almatary wrote:<br>
> > > Hello Padmarao,<br>
> > > <br>
> > > It would be great to have support for running RTEMS on PolarFire.<br>
> > > <br>
> > > I had a quick look at the code. There is a lot of code<br>
> > > duplications<br>
> > > already. The generic RISC-V BSP already has SMP, CLINT, PLIC, and<br>
> > > 16550 support. Why can't this code be shared (i.e., if you use<br>
> > > the<br>
> > > riscv/riscv BSP and just provide your FDT)?<br>
> > > <br>
> > > I'd also try to avoid introducing platform-dependent #ifdefs in<br>
> > > shared<br>
> > > code (e.g., start.S).<br>
> > > <br>
> > > Cheers,<br>
> > > Hesham<br>
> > > <br>
> > > On Wed, 24 Aug 2022 at 08:14, <<a href="mailto:Padmarao.Begari@microchip.com" target="_blank">Padmarao.Begari@microchip.com</a>><br>
> > > wrote:<br>
> > > > Hi,<br>
> > > > <br>
> > > > I want to add a new BSP for RISC-V-based Microchip PolarFire<br>
> > > > SoC(MPFS)<br>
> > > > to RTEMS.<br>
> > > > <br>
> > > > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and a 64-<br>
> > > > bit<br>
> > > > RISC-<br>
> > > > V<br>
> > > > E51 monitor core SoC from Microchip.<br>
> > > > <br>
> > > > The new BSP is added for the U54 cores not for E51 because the<br>
> > > > E51<br>
> > > > moniter core is resreved for first stage bootloader (Hart<br>
> > > > Software<br>
> > > > Services).<br>
> > > > <br>
> > > > This BSP supports below components:<br>
> > > > <br>
> > > > 4 CPU Cores (U54)<br>
> > > > Interrupt controller (PLIC)<br>
> > > > Timer (CLINT)<br>
> > > > UART (mmuart, 16550-compatible)<br>
> > > > <br>
> > > > We have already done some work on this and tested but not with<br>
> > > > latest<br>
> > > > RTEMS source(8th March, 2022 commit) and want to send patches<br>
> > > > with<br>
> > > > latest source.<br>
> > > > <br>
> > > > <a href="https://github.com/polarfire-soc/rtems/tree/mpfs-rtems" rel="noreferrer" target="_blank">
https://github.com/polarfire-soc/rtems/tree/mpfs-rtems</a><br>
> > > > <br>
> > > > Regards<br>
> > > > Padmarao<br>
> > > > _______________________________________________<br>
> > > > users mailing list<br>
> > > > <a href="mailto:users@rtems.org" target="_blank">users@rtems.org</a><br>
> > > > <a href="http://lists.rtems.org/mailman/listinfo/users" rel="noreferrer" target="_blank">
http://lists.rtems.org/mailman/listinfo/users</a><br>
> > _______________________________________________<br>
> > users mailing list<br>
> > <a href="mailto:users@rtems.org" target="_blank">users@rtems.org</a><br>
> > <a href="http://lists.rtems.org/mailman/listinfo/users" rel="noreferrer" target="_blank">
http://lists.rtems.org/mailman/listinfo/users</a><br>
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