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<p class="MsoNormal">I haven’t used the Q8 board, but I have tested the ZU3EG BSP on at least 3 different processor variants (including the dual-core CG variant) across about 5 boards and it has worked without issue. Be warned that u-boot doesn’t support elf64
(or didn’t last time I checked), so you’ll need to package it as a raw binary inside a u-boot image. This is the script I use to accomplish that:<o:p></o:p></p>
<p class="MsoNormal">$ cat create_image.sh<o:p></o:p></p>
<p class="MsoNormal">#!/bin/sh<o:p></o:p></p>
<p class="MsoNormal">aarch64-rtems6-objcopy -O binary "$1" rtems.bin<o:p></o:p></p>
<p class="MsoNormal">gzip -f rtems.bin<o:p></o:p></p>
<p class="MsoNormal">ENTRY=`aarch64-rtems6-nm $1 |grep \ _start|sed -e 's/ .*//'`<o:p></o:p></p>
<p class="MsoNormal">mkimage -A arm64 -O rtems -T kernel -C gzip -a 0x$ENTRY -e 0x$ENTRY -n "$(basename $1)" -d rtems.bin.gz rtems.img<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I tend to load the image via TFTP for testing to avoid write cycles on the flash and for faster turnaround during development.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I suspect that the Q8 might have some system control and other interfaces exposed via the FPGA fabric similar to the CFC-400X, so that will need some extra work to support properly.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Let me know if you have any further questions.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Kinsey<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-left:35.4pt"><b>From:</b> users <users-bounces@rtems.org>
<b>On Behalf Of </b>Schweikhardt, Jens (TSPCE6-TL5)<br>
<b>Sent:</b> Thursday, March 30, 2023 4:03 AM<br>
<b>To:</b> users@rtems.org<br>
<b>Subject:</b> Anyone using Xiphos Q8 (Zynq UltraScale+ MPSoc)?<o:p></o:p></p>
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<p class="MsoNormal" style="margin-left:35.4pt"><o:p> </o:p></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span lang="DE" style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">Hello, world<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span lang="DE" style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">Is anyone using Xiphos’s Q8 boards? It features a Zynq UltraScale+ MPSoC and<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">out of the box comes with an SDK for Yocto Linux 2.5 (sumo).<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">I realize RTEMS has some support for a BSP using the Zynq UltraScale+.<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">I wonder what the challenges would be using RTEMS instead of Linux.<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">Is it more than replacing a Linux rootfs image with an RTEMS application image,<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif">providing a device tree and booting via Xilinx’s uboot?<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span style="font-size:12.0pt;font-family:"Tw Cen MT",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span lang="DE" style="mso-fareast-language:DE">Regards,<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span lang="DE" style="mso-fareast-language:DE">Jens<o:p></o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span lang="DE"><o:p> </o:p></span></p>
<p class="MsoNormal" style="margin-left:35.4pt"><span lang="DE"><o:p> </o:p></span></p>
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