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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">Thanks for bringing this up. I couldn’t find the exact wording you mentioned, but I think this is what you’re referring to in the current (K.a) revision
of the ARM Architecture reference manual for ARMv8:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">D1.3.2 Exception entry<o:p></o:p></span></b></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">When an exception is taken to an Exception level, ELx, that is using AArch64 state, all the following occur:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• The contents of PSTATE immediately before the exception was taken is written to SPSR_ELx.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• The preferred exception return address is written to ELR_ELx.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• The contents of PSTATE immediately after the exception is taken is as described in rule RWTXBY.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• For synchronous exceptions and SError interrupts, exception syndrome information is written to ESR_ELx.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• Execution starts from the exception vector at the target Exception level.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">When an exception is taken to an Exception level, ELx, that is using AArch64 state, after recording the previous<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">values in SPSR_ELx, the following PSTATE bits are set:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• PSTATE.EL is set to the target Exception level.<o:p></o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">• All of PSTATE.{D, A, I, F, SP, TCO, PM} are set to 1.<o:p></o:p></span></b></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">…<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">It’s likely that this is transparently working by accident since nested interrupts occur and any stack usage is unrolled/undone before any dispatching
can occur. The one place where this might actually show up as an issue is when the thread stack pointer is corrupted/misaligned, but that would trigger a non-irq exception which follows a different code path and likely does not allow for nested interrupts.
This has been written up as an issue on the RTEMS GitLab instance: <a href="https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5140">
https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5140</a><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US">Kinsey<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Aptos",sans-serif;mso-fareast-language:EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal" style="margin-left:.5in"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> users <users-bounces@rtems.org>
<b>On Behalf Of </b>lichx2@sugon.com<br>
<b>Sent:</b> Sunday, October 27, 2024 22:09<br>
<b>To:</b> rtems-users@rtems.org<br>
<b>Subject:</b> aarch64 curr_el_sp0_irq/_AArch64_Exception_interrupt_nest use Incorrect sp<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-left:.5in"><o:p> </o:p></p>
<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10.0pt;font-family:"Verdana",sans-serif">Hi</span><span lang="ZH-CN" style="font-size:10.0pt">：</span><span style="font-size:10.0pt;font-family:"Verdana",sans-serif"><o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-left:.5in"><span style="font-size:10.0pt;font-family:"Verdana",sans-serif"> curr_el_sp0_irq/_AArch64_Exception_interrupt_nest may use Incorrect sp. ARM-ARM described "on exception entry to Elx, SP_ELx is automatically
selected. so when curr_el_sp0_irq/_AArch64_Exception_interrupt_nest will use sp_el1(this is task sp not interrupt sp) . Use gdb to verify curr_el_sp0_irq/_AArch64_Exception_interrupt_nest really use Incorrect sp.<o:p></o:p></span></p>
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