[rtems commit] arm: Add ARMv7-M SHCSR register bits
Sebastian Huber
sebh at rtems.org
Fri Jan 10 20:38:07 UTC 2014
Module: rtems
Branch: master
Commit: 805ef2f2baf0dd5cdcd828a36ce5be722407ca25
Changeset: http://git.rtems.org/rtems/commit/?id=805ef2f2baf0dd5cdcd828a36ce5be722407ca25
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Sat Nov 30 20:53:41 2013 +0100
arm: Add ARMv7-M SHCSR register bits
---
cpukit/score/cpu/arm/rtems/score/armv7m.h | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/armv7m.h b/cpukit/score/cpu/arm/rtems/score/armv7m.h
index 3a41a0c..e765dfd 100644
--- a/cpukit/score/cpu/arm/rtems/score/armv7m.h
+++ b/cpukit/score/cpu/arm/rtems/score/armv7m.h
@@ -81,10 +81,16 @@ typedef struct {
#define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1)
#define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0)
uint32_t aircr;
+
uint32_t scr;
uint32_t ccr;
uint8_t shpr [12];
+
+#define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18)
+#define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17)
+#define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16)
uint32_t shcsr;
+
uint32_t cfsr;
uint32_t hfsr;
uint32_t dfsr;
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