[rtems-central commit] spec: Expand GRCLKGATE register bit fields

[Sebastian Huber]

Module:    rtems-central
Branch:    master
Commit:    b46ff7e51ce611d87e0519128382612890689c39
Changeset: http://git.rtems.org/rtems-central/commit/?id=b46ff7e51ce611d87e0519128382612890689c39

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Wed Jul 12 08:16:15 2023 +0200

spec: Expand GRCLKGATE register bit fields

Use the maximum width supported by the GRLIB even if this exceeds the
configuration limits of a particular IP instance.

Update #4842.

---

 spec/dev/grlib/if/grclkgate.yml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/spec/dev/grlib/if/grclkgate.yml b/spec/dev/grlib/if/grclkgate.yml
index 4cdb3688..1be79f79 100644
--- a/spec/dev/grlib/if/grclkgate.yml
+++ b/spec/dev/grlib/if/grclkgate.yml
@@ -46,7 +46,7 @@ registers:
       description: null
       name: 'UNLOCK'
       start: 0
-      width: 11
+      width: 32
     variants: []
   brief: |
     Unlock register
@@ -60,7 +60,7 @@ registers:
       description: null
       name: 'ENABLE'
       start: 0
-      width: 11
+      width: 32
     variants: []
   brief: |
     Clock enable register
@@ -74,7 +74,7 @@ registers:
       description: null
       name: 'RESET'
       start: 0
-      width: 11
+      width: 32
     variants: []
   brief: |
     Reset register