[rtems commit] bsps/arm: Improve GICv3 support

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    5ce7ed1feac7f1943cf7faef006e488fd104f4b3
Changeset: http://git.rtems.org/rtems/commit/?id=5ce7ed1feac7f1943cf7faef006e488fd104f4b3

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Apr 16 10:20:48 2024 +0200

bsps/arm: Improve GICv3 support

In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.

Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.

---

 bsps/shared/dev/irq/arm-gicv3.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index fd7abd6a13..958b1061bd 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -42,12 +42,18 @@
 
 void bsp_interrupt_dispatch(void)
 {
-  uint32_t icciar = READ_SR(ICC_IAR1);
-  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
-  rtems_vector_number spurious = 1023;
+  while (true) {
+    uint32_t icciar = READ_SR(ICC_IAR1);
+    rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+    uint32_t status;
 
-  if (vector != spurious) {
-    arm_interrupt_handler_dispatch(vector);
+    if (!bsp_interrupt_is_valid_vector(vector)) {
+      break;
+    }
+
+    status = arm_interrupt_enable_interrupts();
+    bsp_interrupt_handler_dispatch_unchecked(vector);
+    arm_interrupt_restore_interrupts(status);
 
     WRITE_SR(ICC_EOIR1, icciar);
   }