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<title>change log for rtems (2011-02-15)</title>
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<font color='#bb2222'><strong>sh</strong></font>
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<tr><td colspan='3' bgcolor='#dddddd'><pre>2011-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
* rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and
MSR_UBLE defines.
</pre></td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/cpukit/score/cpu/powerpc/ChangeLog.diff?r1=text&tr1=1.161&r2=text&tr2=1.162&diff_format=h">M</a></td><td width='1%'>1.162</td><td width='100%'>cpukit/score/cpu/powerpc/ChangeLog</td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h.diff?r1=text&tr1=1.35&r2=text&tr2=1.36&diff_format=h">M</a></td><td width='1%'>1.36</td><td width='100%'>cpukit/score/cpu/powerpc/rtems/powerpc/registers.h</td></tr>
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<font color='#006600'>diff -u rtems/cpukit/score/cpu/powerpc/ChangeLog:1.161 rtems/cpukit/score/cpu/powerpc/ChangeLog:1.162
--- rtems/cpukit/score/cpu/powerpc/ChangeLog:1.161 Fri Feb 11 03:24:09 2011
+++ rtems/cpukit/score/cpu/powerpc/ChangeLog Tue Feb 15 01:45:16 2011
</font><font color='#997700'>@@ -1,3 +1,8 @@
</font><font color='#000088'>+2011-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ * rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and
+ MSR_UBLE defines.
+
</font> 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/powerpc/registers.h, rtems/score/cpu.h:
<font color='#006600'>diff -u rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.35 rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.36
--- rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.35 Fri Feb 11 03:24:09 2011
+++ rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h Tue Feb 15 01:45:16 2011
</font><font color='#997700'>@@ -19,8 +19,11 @@
</font> #define _RTEMS_POWERPC_REGISTERS_H
/* Bit encodings for Machine State Register (MSR) */
<font color='#000088'>+#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
</font> #define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */
<font color='#000088'>+#define MSR_SPE (1<<25) /* SPE enable (e500) */
</font> #define MSR_POW (1<<18) /* Enable Power Management */
<font color='#000088'>+#define MSR_WE (1<<18) /* Wait state enable (e500) */
</font> #define MSR_TGPR (1<<17) /* TLB Update registers in use */
#define MSR_CE (1<<17) /* BookE critical interrupt */
#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
<font color='#997700'>@@ -30,6 +33,7 @@
</font> #define MSR_ME (1<<12) /* Machine Check enable */
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
#define MSR_SE (1<<10) /* Single Step */
<font color='#000088'>+#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */
</font> #define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* BookE debug exception */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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