<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>change log for rtems (2011-06-21)</title>
</head>
<body text='#000000' bgcolor='#ffffff'>
<a name='cs1'></a>
<table border='0' cellspacing='0' cellpadding='5' width='100%' bgcolor='#eeeeee'>
<tr><td colspan='3' bgcolor='#dddddd'>
<font color='#bb2222'><strong>joel</strong></font>
</td></tr>
<tr><td colspan='3' bgcolor='#dddddd'><pre>2011-06-21 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/score/cpu.h, rtems/score/sparc.h, rtems/score/types.h: Convert
comments to Doxygen style and improve.
</pre></td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/cpukit/score/cpu/sparc/ChangeLog.diff?r1=text&tr1=1.103&r2=text&tr2=1.104&diff_format=h">M</a></td><td width='1%'>1.104</td><td width='100%'>cpukit/score/cpu/sparc/ChangeLog</td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h.diff?r1=text&tr1=1.40&r2=text&tr2=1.41&diff_format=h">M</a></td><td width='1%'>1.41</td><td width='100%'>cpukit/score/cpu/sparc/rtems/score/cpu.h</td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h.diff?r1=text&tr1=1.16&r2=text&tr2=1.17&diff_format=h">M</a></td><td width='1%'>1.17</td><td width='100%'>cpukit/score/cpu/sparc/rtems/score/sparc.h</td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/cpukit/score/cpu/sparc/rtems/score/types.h.diff?r1=text&tr1=1.18&r2=text&tr2=1.19&diff_format=h">M</a></td><td width='1%'>1.19</td><td width='100%'>cpukit/score/cpu/sparc/rtems/score/types.h</td></tr>
</table>
<pre>
<font color='#006600'>diff -u rtems/cpukit/score/cpu/sparc/ChangeLog:1.103 rtems/cpukit/score/cpu/sparc/ChangeLog:1.104
--- rtems/cpukit/score/cpu/sparc/ChangeLog:1.103 Tue May 17 09:51:33 2011
+++ rtems/cpukit/score/cpu/sparc/ChangeLog Tue Jun 21 17:12:10 2011
</font><font color='#997700'>@@ -1,3 +1,8 @@
</font><font color='#000088'>+2011-06-21 Joel Sherrill <joel.sherrill@oarcorp.com>
+
+ * rtems/score/cpu.h, rtems/score/sparc.h, rtems/score/types.h: Convert
+ comments to Doxygen style and improve.
+
</font> 2011-05-17 Ralf Corsépius <ralf.corsepius@rtems.org>
* Makefile.am: Reformat.
<font color='#006600'>diff -u rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h:1.40 rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h:1.41
--- rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h:1.40 Wed Mar 16 15:05:05 2011
+++ rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h Tue Jun 21 17:12:10 2011
</font><font color='#997700'>@@ -1,11 +1,11 @@
</font> /**
* @file rtems/score/cpu.h
<font color='#000088'>+ *
+ * This include file contains information pertaining to the port of
+ * the executive to the SPARC processor.
</font> */
/*
<font color='#880000'>- * This include file contains information pertaining to the port of
- * the executive to the SPARC processor.
- *
</font> * COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*
<font color='#997700'>@@ -28,33 +28,33 @@
</font>
/* conditional compilation parameters */
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Should the calls to _Thread_Enable_dispatch be inlined?
*
<font color='#880000'>- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
</font><font color='#000088'>+ * - If TRUE, then they are inlined.
+ * - If FALSE, then a subroutine call is made.
+ *
+ * On this port, it is faster to inline _Thread_Enable_dispatch.
</font> */
<font color='#880000'>-
</font> #define CPU_INLINE_ENABLE_DISPATCH TRUE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
<font color='#880000'>- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
</font><font color='#000088'>+ * - If TRUE, then the loops are unrolled.
+ * - If FALSE, then the loops are not unrolled.
</font> *
* This parameter could go either way on the SPARC. The interrupt flash
* code is relatively lengthy given the requirements for nops following
* writes to the psr. But if the clock speed were high enough, this would
* not represent a great deal of time.
*/
<font color='#880000'>-
</font> #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Does the executive manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _ISR_Handler_initialization.
<font color='#997700'>@@ -63,126 +63,141 @@
</font> * The SPARC does not have a dedicated HW interrupt stack and one has
* been implemented in SW.
*/
<font color='#880000'>-
</font> #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Does the CPU follow the simple vectored interrupt model?
*
<font color='#880000'>- * If TRUE, then RTEMS allocates the vector table it internally manages.
- * If FALSE, then the BSP is assumed to allocate and manage the vector
- * table
- *
- * SPARC Specific Information:
</font><font color='#000088'>+ * - If TRUE, then RTEMS allocates the vector table it internally manages.
+ * - If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
</font> *
<font color='#880000'>- * XXX document implementation including references if appropriate
</font><font color='#000088'>+ * THe SPARC is a simple vectored architecture. Usually there is no
+ * PIC and the CPU directly vectors the interrupts.
</font> */
#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
<font color='#880000'>-/*
</font><font color='#000088'>+/**<span style="background-color: #FF0000"> </span>
</font> * Does this CPU have hardware support for a dedicated interrupt stack?
*
<font color='#880000'>- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
</font><font color='#000088'>+ * - If TRUE, then it must be installed during initialization.
+ * - If FALSE, then no installation is performed.
</font> *
* The SPARC does not have a dedicated HW interrupt stack.
*/
<font color='#880000'>-
</font> #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Do we allocate a dedicated interrupt stack in the Interrupt Manager?
*
<font color='#880000'>- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
</font><font color='#000088'>+ * - If TRUE, then the memory is allocated during initialization.
+ * - If FALSE, then the memory is allocated during initialization.
+ *
+ * The SPARC does not have hardware support for switching to a<span style="background-color: #FF0000"> </span>
+ * dedicated interrupt stack. The port includes support for doing this
+ * in software.
+ *
</font> */
<font color='#880000'>-
</font> #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
<font color='#000088'>+ *
+ * The SPARC port does not pass an Interrupt Stack Frame pointer to
+ * interrupt handlers.
</font> */
<font color='#880000'>-
</font> #define CPU_ISR_PASSES_FRAME_POINTER 0
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Does the CPU have hardware floating point?
*
<font color='#880000'>- * If TRUE, then the FLOATING_POINT task attribute is supported.
- * If FALSE, then the FLOATING_POINT task attribute is ignored.
</font><font color='#000088'>+ * - If TRUE, then the FLOATING_POINT task attribute is supported.
+ * - If FALSE, then the FLOATING_POINT task attribute is ignored.
+ *
+ * This is set based upon the multilib settings.
</font> */
<font color='#880000'>-
</font> #if ( SPARC_HAS_FPU == 1 )
<font color='#880000'>-#define CPU_HARDWARE_FP TRUE
</font><font color='#000088'>+ #define CPU_HARDWARE_FP TRUE
</font> #else
<font color='#880000'>-#define CPU_HARDWARE_FP FALSE
</font><font color='#000088'>+ #define CPU_HARDWARE_FP FALSE
</font> #endif
<font color='#000088'>+
+/**
+ * The SPARC GCC port does not have a software floating point library
+ * that requires RTEMS assistance.
+ */
</font> #define CPU_SOFTWARE_FP FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Are all tasks FLOATING_POINT tasks implicitly?
*
<font color='#880000'>- * If TRUE, then the FLOATING_POINT task attribute is assumed.
- * If FALSE, then the FLOATING_POINT task attribute is followed.
</font><font color='#000088'>+ * - If TRUE, then the FLOATING_POINT task attribute is assumed.
+ * - If FALSE, then the FLOATING_POINT task attribute is followed.
+ *
+ * The SPARC GCC port does not implicitly use floating point registers.
</font> */
<font color='#880000'>-
</font> #define CPU_ALL_TASKS_ARE_FP FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Should the IDLE task have a floating point context?
*
<font color='#880000'>- * If TRUE, then the IDLE task is created as a FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
</font><font color='#000088'>+ * - If TRUE, then the IDLE task is created as a FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * - If FALSE, then the IDLE task does not have a floating point context.
+ *
+ * The IDLE task does not have to be floating point on the SPARC.
</font> */
<font color='#880000'>-
</font> #define CPU_IDLE_TASK_IS_FP FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
<font color='#880000'>- * If TRUE, then the floating point context will not be stored until
</font><font color='#000088'>+ * - If TRUE, then the floating point context will not be stored until
</font> * necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
<font color='#880000'>- * If FALSE, then the floating point context is saved when a floating
</font><font color='#000088'>+ * - If FALSE, then the floating point context is saved when a floating
</font> * point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
<font color='#000088'>+ *
+ * On the SPARC, we can disable the FPU for integer only tasks so
+ * it is safe to defer floating point context switches.
</font> */
<font color='#880000'>-
</font> #define CPU_USE_DEFERRED_FP_SWITCH TRUE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Does this port provide a CPU dependent IDLE task implementation?
*
<font color='#880000'>- * If TRUE, then the routine _CPU_Thread_Idle_body
</font><font color='#000088'>+ * - If TRUE, then the routine _CPU_Thread_Idle_body
</font> * must be provided and is the default IDLE thread body instead of
* _CPU_Thread_Idle_body.
*
<font color='#880000'>- * If FALSE, then use the generic IDLE thread body if the BSP does
</font><font color='#000088'>+ * - If FALSE, then use the generic IDLE thread body if the BSP does
</font> * not provide one.
<font color='#000088'>+ *
+ * The SPARC architecture does not have a low power or halt instruction.
+ * It is left to the BSP and/or CPU specific code to provide an IDLE
+ * thread body which is aware of low power modes.
</font> */
<font color='#880000'>-
</font> #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
<font color='#880000'>- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
</font><font color='#000088'>+ * - If TRUE, then the grows upward.
+ * - If FALSE, then the grows toward smaller addresses.
</font> *
* The stack grows to lower addresses on the SPARC.
*/
<font color='#880000'>-
</font> #define CPU_STACK_GROWS_UP FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * The following is the variable attribute used to force alignment
* of critical data structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
<font color='#997700'>@@ -192,107 +207,161 @@
</font> * The SPARC does not appear to have particularly strict alignment
* requirements. This value was chosen to take advantages of caches.
*/
<font color='#880000'>-
</font> #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Define what is required to specify how the network to host conversion
* routines are handled.
<font color='#000088'>+ *
+ * The SPARC is big endian.
</font> */
<font color='#880000'>-
</font> #define CPU_BIG_ENDIAN TRUE
<font color='#000088'>+
+/**
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
+ *
+ * The SPARC is NOT little endian.
+ */
</font> #define CPU_LITTLE_ENDIAN FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*
* The SPARC has 16 interrupt levels in the PIL field of the PSR.
*/
<font color='#880000'>-
</font> #define CPU_MODES_INTERRUPT_MASK 0x0000000F
<font color='#880000'>-/*
</font><font color='#000088'>+#ifndef ASM
+/**
</font> * This structure represents the organization of the minimum stack frame
* for the SPARC. More framing information is required in certain situaions
* such as when there are a large number of out parameters or when the callee
* must save floating point registers.
*/
<font color='#880000'>-
-#ifndef ASM
-
</font> typedef struct {
<font color='#000088'>+ /** This is the offset of the l0 register. */
</font> uint32_t l0;
<font color='#000088'>+ /** This is the offset of the l1 register. */
</font> uint32_t l1;
<font color='#000088'>+ /** This is the offset of the l2 register. */
</font> uint32_t l2;
<font color='#000088'>+ /** This is the offset of the l3 register. */
</font> uint32_t l3;
<font color='#000088'>+ /** This is the offset of the l4 register. */
</font> uint32_t l4;
<font color='#000088'>+ /** This is the offset of the l5 register. */
</font> uint32_t l5;
<font color='#000088'>+ /** This is the offset of the l6 register. */
</font> uint32_t l6;
<font color='#000088'>+ /** This is the offset of the l7 register. */
</font> uint32_t l7;
<font color='#000088'>+ /** This is the offset of the l0 register. */
</font> uint32_t i0;
<font color='#000088'>+ /** This is the offset of the i1 register. */
</font> uint32_t i1;
<font color='#000088'>+ /** This is the offset of the i2 register. */
</font> uint32_t i2;
<font color='#000088'>+ /** This is the offset of the i3 register. */
</font> uint32_t i3;
<font color='#000088'>+ /** This is the offset of the i4 register. */
</font> uint32_t i4;
<font color='#000088'>+ /** This is the offset of the i5 register. */
</font> uint32_t i5;
<font color='#000088'>+ /** This is the offset of the i6 register. */
</font> uint32_t i6_fp;
<font color='#000088'>+ /** This is the offset of the i7 register. */
</font> uint32_t i7;
<font color='#000088'>+ /** This is the offset of the register used to return structures. */
</font> void *structure_return_address;
<font color='#000088'>+
</font> /*
* The following are for the callee to save the register arguments in
* should this be necessary.
*/
<font color='#000088'>+ /** This is the offset of the register for saved argument 0. */
</font> uint32_t saved_arg0;
<font color='#000088'>+ /** This is the offset of the register for saved argument 1. */
</font> uint32_t saved_arg1;
<font color='#000088'>+ /** This is the offset of the register for saved argument 2. */
</font> uint32_t saved_arg2;
<font color='#000088'>+ /** This is the offset of the register for saved argument 3. */
</font> uint32_t saved_arg3;
<font color='#000088'>+ /** This is the offset of the register for saved argument 4. */
</font> uint32_t saved_arg4;
<font color='#000088'>+ /** This is the offset of the register for saved argument 5. */
</font> uint32_t saved_arg5;
<font color='#000088'>+ /** This field pads the structure so ldd and std instructions can be used. */
</font> uint32_t pad0;
} CPU_Minimum_stack_frame;
#endif /* ASM */
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L0_OFFSET 0x00
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L1_OFFSET 0x04
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L2_OFFSET 0x08
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L3_OFFSET 0x0c
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L4_OFFSET 0x10
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L5_OFFSET 0x14
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L6_OFFSET 0x18
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_L7_OFFSET 0x1c
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I0_OFFSET 0x20
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I1_OFFSET 0x24
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I2_OFFSET 0x28
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I3_OFFSET 0x2c
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I4_OFFSET 0x30
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I5_OFFSET 0x34
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_I7_OFFSET 0x3c
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58
<font color='#000088'>+/** This macro defines an offset into the stack frame for use in assembly. */
</font> #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
<font color='#000088'>+/** This defines the size of the minimum stack frame. */
</font> #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
<font color='#880000'>-/*
- * Contexts
</font><font color='#000088'>+/**
+ * @defgroup Contexts SPARC Context Structures
</font> *
* Generally there are 2 types of context to save.
<font color='#880000'>- * 1. Interrupt registers to save
- * 2. Task level registers to save
</font><font color='#000088'>+ * + Interrupt registers to save
+ * + Task level registers to save
</font> *
* This means we have the following 3 context items:
<font color='#880000'>- * 1. task level context stuff:: Context_Control
- * 2. floating point task stuff:: Context_Control_fp
- * 3. special interrupt level context :: Context_Control_interrupt
</font><font color='#000088'>+ * + task level context stuff:: Context_Control
+ * + floating point task stuff:: Context_Control_fp
+ * + special interrupt level context :: Context_Control_interrupt
</font> *
* On the SPARC, we are relatively conservative in that we save most
* of the CPU state in the context area. The ET (enable trap) bit and
<font color='#997700'>@@ -301,52 +370,100 @@
</font> */
#ifndef ASM
<font color='#880000'>-
</font><font color='#000088'>+/**
+ * @brief SPARC Basic Context
+ *
+ * @ingroup Contexts
+ *
+ * This structure defines the basic integer and processor state context
+ * for the SPARC architecture.
+ */
</font> typedef struct {
<font color='#880000'>- /*
- * Using a double g0_g1 will put everything in this structure on a
- * double word boundary which allows us to use double word loads
- * and stores safely in the context switch.
- */
- double g0_g1;
- uint32_t g2;
- uint32_t g3;
- uint32_t g4;
- uint32_t g5;
- uint32_t g6;
- uint32_t g7;
-
- uint32_t l0;
- uint32_t l1;
- uint32_t l2;
- uint32_t l3;
- uint32_t l4;
- uint32_t l5;
- uint32_t l6;
- uint32_t l7;
-
- uint32_t i0;
- uint32_t i1;
- uint32_t i2;
- uint32_t i3;
- uint32_t i4;
- uint32_t i5;
- uint32_t i6_fp;
- uint32_t i7;
-
- uint32_t o0;
- uint32_t o1;
- uint32_t o2;
- uint32_t o3;
- uint32_t o4;
- uint32_t o5;
- uint32_t o6_sp;
- uint32_t o7;
-
- uint32_t psr;
- uint32_t isr_dispatch_disable;
</font><font color='#000088'>+ /**
+ * Using a double g0_g1 will put everything in this structure on a
+ * double word boundary which allows us to use double word loads
+ * and stores safely in the context switch.
+ */
+ double g0_g1;
+ /** This will contain the contents of the g2 register. */
+ uint32_t g2;
+ /** This will contain the contents of the g3 register. */
+ uint32_t g3;
+ /** This will contain the contents of the g4 register. */
+ uint32_t g4;
+ /** This will contain the contents of the g5 register. */
+ uint32_t g5;
+ /** This will contain the contents of the g6 register. */
+ uint32_t g6;
+ /** This will contain the contents of the g7 register. */
+ uint32_t g7;
+
+ /** This will contain the contents of the l0 register. */
+ uint32_t l0;
+ /** This will contain the contents of the l1 register. */
+ uint32_t l1;
+ /** This will contain the contents of the l2 register. */
+ uint32_t l2;
+ /** This will contain the contents of the l3 register. */
+ uint32_t l3;
+ /** This will contain the contents of the l4 register. */
+ uint32_t l4;
+ /** This will contain the contents of the l5 registeer.*/
+ uint32_t l5;
+ /** This will contain the contents of the l6 register. */
+ uint32_t l6;
+ /** This will contain the contents of the l7 register. */
+ uint32_t l7;
+
+ /** This will contain the contents of the i0 register. */
+ uint32_t i0;
+ /** This will contain the contents of the i1 register. */
+ uint32_t i1;
+ /** This will contain the contents of the i2 register. */
+ uint32_t i2;
+ /** This will contain the contents of the i3 register. */
+ uint32_t i3;
+ /** This will contain the contents of the i4 register. */
+ uint32_t i4;
+ /** This will contain the contents of the i5 register. */
+ uint32_t i5;
+ /** This will contain the contents of the i6 (e.g. frame pointer) register. */
+ uint32_t i6_fp;
+ /** This will contain the contents of the i7 register. */
+ uint32_t i7;
+
+ /** This will contain the contents of the o0 register. */
+ uint32_t o0;
+ /** This will contain the contents of the o1 register. */
+ uint32_t o1;
+ /** This will contain the contents of the o2 register. */
+ uint32_t o2;
+ /** This will contain the contents of the o3 register. */
+ uint32_t o3;
+ /** This will contain the contents of the o4 register. */
+ uint32_t o4;
+ /** This will contain the contents of the o5 register. */
+ uint32_t o5;
+ /** This will contain the contents of the o6 (e.g. frame pointer) register. */
+ uint32_t o6_sp;
+ /** This will contain the contents of the o7 register. */
+ uint32_t o7;
+
+ /** This will contain the contents of the processor status register. */
+ uint32_t psr;
+ /**
+ * This field is used to prevent heavy nesting of calls to _Thread_Dispatch
+ * on an interrupted task's stack. This is problematic on the slower
+ * SPARC CPU models at high interrupt rates.
+ */
+ uint32_t isr_dispatch_disable;
</font> } Context_Control;
<font color='#000088'>+/**
+ * This macro provides a CPU independent way for RTEMS to access the
+ * stack pointer in a context structure. The actual name and offset is
+ * CPU architecture dependent.
+ */
</font> #define _CPU_Context_Get_SP( _context ) \
(_context)->o6_sp
<font color='#997700'>@@ -356,71 +473,125 @@
</font> * Offsets of fields with Context_Control for assembly routines.
*/
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G0_OFFSET 0x00
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G1_OFFSET 0x04
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G2_OFFSET 0x08
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G3_OFFSET 0x0C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G4_OFFSET 0x10
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G5_OFFSET 0x14
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G6_OFFSET 0x18
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define G7_OFFSET 0x1C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L0_OFFSET 0x20
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L1_OFFSET 0x24
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L2_OFFSET 0x28
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L3_OFFSET 0x2C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L4_OFFSET 0x30
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L5_OFFSET 0x34
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L6_OFFSET 0x38
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define L7_OFFSET 0x3C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I0_OFFSET 0x40
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I1_OFFSET 0x44
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I2_OFFSET 0x48
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I3_OFFSET 0x4C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I4_OFFSET 0x50
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I5_OFFSET 0x54
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I6_FP_OFFSET 0x58
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define I7_OFFSET 0x5C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O0_OFFSET 0x60
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O1_OFFSET 0x64
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O2_OFFSET 0x68
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O3_OFFSET 0x6C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O4_OFFSET 0x70
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O5_OFFSET 0x74
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O6_SP_OFFSET 0x78
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define O7_OFFSET 0x7C
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define PSR_OFFSET 0x80
<font color='#000088'>+/** This macro defines an offset into the context for use in assembly. */
</font> #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
<font color='#000088'>+/** This defines the size of the context area for use in assembly. */
</font> #define CONTEXT_CONTROL_SIZE 0x88
<font color='#880000'>-/*
- * The floating point context area.
- */
-
</font> #ifndef ASM
<font color='#880000'>-
</font><font color='#000088'>+/**
+ * @brief SPARC Basic Context
+ *
+ * @ingroup Contexts
+ *
+ * This structure defines floating point context area.
+ */
</font> typedef struct {
<font color='#880000'>- double f0_f1;
- double f2_f3;
- double f4_f5;
- double f6_f7;
- double f8_f9;
- double f10_f11;
- double f12_f13;
- double f14_f15;
- double f16_f17;
- double f18_f19;
- double f20_f21;
- double f22_f23;
- double f24_f25;
- double f26_f27;
- double f28_f29;
- double f30_f31;
- uint32_t fsr;
</font><font color='#000088'>+ /** This will contain the contents of the f0 and f1 register. */
+ double f0_f1;
+ /** This will contain the contents of the f2 and f3 register. */
+ double f2_f3;
+ /** This will contain the contents of the f4 and f5 register. */
+ double f4_f5;
+ /** This will contain the contents of the f6 and f7 register. */
+ double f6_f7;
+ /** This will contain the contents of the f8 and f9 register. */
+ double f8_f9;
+ /** This will contain the contents of the f10 and f11 register. */
+ double f10_f11;
+ /** This will contain the contents of the f12 and f13 register. */
+ double f12_f13;
+ /** This will contain the contents of the f14 and f15 register. */
+ double f14_f15;
+ /** This will contain the contents of the f16 and f17 register. */
+ double f16_f17;
+ /** This will contain the contents of the f18 and f19 register. */
+ double f18_f19;
+ /** This will contain the contents of the f20 and f21 register. */
+ double f20_f21;
+ /** This will contain the contents of the f22 and f23 register. */
+ double f22_f23;
+ /** This will contain the contents of the f24 and f25 register. */
+ double f24_f25;
+ /** This will contain the contents of the f26 and f27 register. */
+ double f26_f27;
+ /** This will contain the contents of the f28 and f29 register. */
+ double f28_f29;
+ /** This will contain the contents of the f30 and f31 register. */
+ double f30_f31;
+ /** This will contain the contents of the floating point status register. */
+ uint32_t fsr;
</font> } Context_Control_fp;
#endif /* ASM */
<font color='#997700'>@@ -429,56 +600,96 @@
</font> * Offsets of fields with Context_Control_fp for assembly routines.
*/
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define FO_F1_OFFSET 0x00
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F2_F3_OFFSET 0x08
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F4_F5_OFFSET 0x10
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F6_F7_OFFSET 0x18
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F8_F9_OFFSET 0x20
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F1O_F11_OFFSET 0x28
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F12_F13_OFFSET 0x30
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F14_F15_OFFSET 0x38
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F16_F17_OFFSET 0x40
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F18_F19_OFFSET 0x48
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F2O_F21_OFFSET 0x50
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F22_F23_OFFSET 0x58
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F24_F25_OFFSET 0x60
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F26_F27_OFFSET 0x68
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F28_F29_OFFSET 0x70
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define F3O_F31_OFFSET 0x78
<font color='#000088'>+/** This macro defines an offset into the FPU context for use in assembly. */
</font> #define FSR_OFFSET 0x80
<font color='#000088'>+/** This defines the size of the FPU context area for use in assembly. */
</font> #define CONTEXT_CONTROL_FP_SIZE 0x84
#ifndef ASM
<font color='#880000'>-/*
</font><font color='#000088'>+/**
+ * @brief Interrupt Stack Frame (ISF)
+ *
</font> * Context saved on stack for an interrupt.
*
<font color='#880000'>- * NOTE: The PSR, PC, and NPC are only saved in this structure for the
- * benefit of the user's handler.
</font><font color='#000088'>+ * @note The PSR, PC, and NPC are only saved in this structure for the
+ * benefit of the user's handler.
</font> */
<font color='#880000'>-
</font> typedef struct {
<font color='#000088'>+ /** On an interrupt, we must save the minimum stack frame. */
</font> CPU_Minimum_stack_frame Stack_frame;
<font color='#000088'>+ /** This is the offset of the PSR on an ISF. */
</font> uint32_t psr;
<font color='#000088'>+ /** This is the offset of the XXX on an ISF. */
</font> uint32_t pc;
<font color='#000088'>+ /** This is the offset of the XXX on an ISF. */
</font> uint32_t npc;
<font color='#000088'>+ /** This is the offset of the g1 register on an ISF. */
</font> uint32_t g1;
<font color='#000088'>+ /** This is the offset of the g2 register on an ISF. */
</font> uint32_t g2;
<font color='#000088'>+ /** This is the offset of the g3 register on an ISF. */
</font> uint32_t g3;
<font color='#000088'>+ /** This is the offset of the g4 register on an ISF. */
</font> uint32_t g4;
<font color='#000088'>+ /** This is the offset of the g5 register on an ISF. */
</font> uint32_t g5;
<font color='#000088'>+ /** This is the offset of the g6 register on an ISF. */
</font> uint32_t g6;
<font color='#000088'>+ /** This is the offset of the g7 register on an ISF. */
</font> uint32_t g7;
<font color='#000088'>+ /** This is the offset of the i0 register on an ISF. */
</font> uint32_t i0;
<font color='#000088'>+ /** This is the offset of the i1 register on an ISF. */
</font> uint32_t i1;
<font color='#000088'>+ /** This is the offset of the i2 register on an ISF. */
</font> uint32_t i2;
<font color='#000088'>+ /** This is the offset of the i3 register on an ISF. */
</font> uint32_t i3;
<font color='#000088'>+ /** This is the offset of the i4 register on an ISF. */
</font> uint32_t i4;
<font color='#000088'>+ /** This is the offset of the i5 register on an ISF. */
</font> uint32_t i5;
<font color='#000088'>+ /** This is the offset of the i6 register on an ISF. */
</font> uint32_t i6_fp;
<font color='#000088'>+ /** This is the offset of the i7 register on an ISF. */
</font> uint32_t i7;
<font color='#000088'>+ /** This is the offset of the y register on an ISF. */
</font> uint32_t y;
<font color='#000088'>+ /** This is the offset of the tpc register on an ISF. */
</font> uint32_t tpc;
} CPU_Interrupt_frame;
<font color='#997700'>@@ -488,64 +699,89 @@
</font> * Offsets of fields with CPU_Interrupt_frame for assembly routines.
*/
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_STACK_FRAME_OFFSET 0x00
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
<font color='#000088'>+/** This macro defines an offset into the ISF for use in assembly. */
</font> #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
<font color='#880000'>-#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
</font><font color='#000088'>+/** This defines the size of the ISF area for use in assembly. */
+#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \
+ CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
+
</font> #ifndef ASM
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This variable is contains the initialize context for the FP unit.
* It is filled in by _CPU_Initialize and copied into the task's FP
* context area during _CPU_Context_Initialize.
*/
<font color='#880000'>-
</font> SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This flag is context switched with each thread. It indicates
* that THIS thread has an _ISR_Dispatch stack frame on its stack.
* By using this flag, we can avoid nesting more interrupt dispatching
* attempts on a previously interrupted thread's stack.
*/
<font color='#880000'>-
</font> SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * The following type defines an entry in the SPARC's trap table.
*
<font color='#880000'>- * NOTE: The instructions chosen are RTEMS dependent although one is
</font><font color='#000088'>+ * @note The instructions chosen are RTEMS dependent although one is
</font> * obligated to use two of the four instructions to perform a
* long jump. The other instructions load one register with the
* trap type (a.k.a. vector) and another with the psr.
*/
<font color='#880000'>-
</font> typedef struct {
<font color='#880000'>- uint32_t mov_psr_l0; /* mov %psr, %l0 */
- uint32_t sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */
- uint32_t jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */
- uint32_t mov_vector_l3; /* mov _vector, %l3 */
</font><font color='#000088'>+ /** This will contain a "mov %psr, %l0" instruction. */
+ uint32_t mov_psr_l0;
+ /** This will contain a "sethi %hi(_handler), %l4" instruction. */
+ uint32_t sethi_of_handler_to_l4;
+ /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */
+ uint32_t jmp_to_low_of_handler_plus_l4;
+ /** This will contain a " mov _vector, %l3" instruction. */
+ uint32_t mov_vector_l3;
</font> } CPU_Trap_table_entry;
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This is the set of opcodes for the instructions loaded into a trap
* table entry. The routine which installs a handler is responsible
* for filling in the fields for the _handler address and the _vector
<font color='#997700'>@@ -554,26 +790,23 @@
</font> * The constants following this structure are masks for the fields which
* must be filled in when the handler is installed.
*/
<font color='#880000'>-
</font> extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * The size of the floating point context area.
*/
<font color='#880000'>-
</font> #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
#endif
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Amount of extra stack (above minimum stack size) required by
* MPCI receive server thread. Remember that in a multiprocessor
* system this thread must exist and be able to process all directives.
*/
<font color='#880000'>-
</font> #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This defines the number of entries in the ISR_Vector_table managed
* by the executive.
*
<font color='#997700'>@@ -596,24 +829,42 @@
</font> * an asynchronous trap. This will avoid the executive changing the return
* address.
*/
<font color='#880000'>-
</font> #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
<font color='#000088'>+
+/**
+ * The SPARC has 256 vectors but the port treats 256-512 as synchronous
+ * traps.
+ */
</font> #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
<font color='#000088'>+/**
+ * This is the bit step in a vector number to indicate it is being installed
+ * as a synchronous trap.
+ */
</font> #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
<font color='#000088'>+
+/**
+ * This macro indicates that @a _trap as an asynchronous trap.
+ */
</font> #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
<font color='#000088'>+
+/**
+ * This macro indicates that @a _trap as a synchronous trap.
+ */
</font> #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 )
<font color='#000088'>+/**
+ * This macro returns the real hardware vector number associated with @a _trap.
+ */
</font> #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256)
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This is defined if the port has a special way to report the ISR nesting
* level. Most ports maintain the variable _ISR_Nest_level.
*/
<font color='#880000'>-
</font> #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Should be large enough to run all tests. This ensures
* that a "reasonable" small application should not have any problems.
*
<font color='#997700'>@@ -621,19 +872,17 @@
</font> * represents a call depth of about 20 routines based on the minimum
* stack frame.
*/
<font color='#880000'>-
</font> #define CPU_STACK_MINIMUM_SIZE (1024*4)
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*
* On the SPARC, this is required for double word loads and stores.
*/
<font color='#880000'>-
</font> #define CPU_ALIGNMENT 8
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
<font color='#997700'>@@ -641,13 +890,12 @@
</font> * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
<font color='#880000'>- * NOTE: This does not have to be a power of 2. It does have to
</font><font color='#000088'>+ * @note This does not have to be a power of 2. It does have to
</font> * be greater or equal to than CPU_ALIGNMENT.
*/
<font color='#880000'>-
</font> #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
<font color='#997700'>@@ -655,26 +903,24 @@
</font> * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
<font color='#880000'>- * NOTE: This does not have to be a power of 2. It does have to
</font><font color='#000088'>+ * @note This does not have to be a power of 2. It does have to
</font> * be greater or equal to than CPU_ALIGNMENT.
*/
<font color='#880000'>-
</font> #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
<font color='#880000'>- * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
</font><font color='#000088'>+ * @note This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
</font> *
* The alignment restrictions for the SPARC are not that strict but this
* should unsure that the stack is always sufficiently alignment that the
* window overflow, underflow, and flush routines can use double word loads
* and stores.
*/
<font color='#880000'>-
</font> #define CPU_STACK_ALIGNMENT 16
#ifndef ASM
<font color='#997700'>@@ -683,68 +929,76 @@
</font> * ISR handler macros
*/
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Support routine to initialize the RTEMS vector table after it is allocated.
*/
<font color='#880000'>-
</font> #define _CPU_Initialize_vectors()
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Disable all interrupts for a critical section. The previous
* level is returned in _level.
*/
<font color='#880000'>-
</font> #define _CPU_ISR_Disable( _level ) \
(_level) = sparc_disable_interrupts()
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of a critical section. The parameter
* _level is not modified.
*/
<font color='#880000'>-
</font> #define _CPU_ISR_Enable( _level ) \
sparc_enable_interrupts( _level )
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
<font color='#880000'>-
</font> #define _CPU_ISR_Flash( _level ) \
sparc_flash_interrupts( _level )
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a straight fashion are undefined.
*/
<font color='#880000'>-
</font> #define _CPU_ISR_Set_level( _newlevel ) \
sparc_enable_interrupts( _newlevel << 8)
<font color='#000088'>+/**
+ * @brief Obtain the Current Interrupt Disable Level
+ *
+ * This method is invoked to return the current interrupt disable level.
+ *
+ * @return This method returns the current interrupt disable level.
+ */<span style="background-color: #FF0000"> </span>
</font> uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
<font color='#880000'>- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
</font><font color='#000088'>+ * - setting a starting address
+ * - preparing the stack
+ * - preparing the stack and frame pointers
+ * - setting the proper interrupt level in the context
+ * - initializing the floating point context
+ *
+ * @param[in] the_context points to the context area
+ * @param[in] stack_base is the low address of the allocated stack area
+ * @param[in] size is the size of the stack area in bytes
+ * @param[in] new_level is the interrupt level for the task
+ * @param[in] entry_point is the task's entry point
+ * @param[in] is_fp is set to TRUE if the task is a floating point task
</font> *
<font color='#880000'>- * NOTE: Implemented as a subroutine for the SPARC port.
</font><font color='#000088'>+ * @note Implemented as a subroutine for the SPARC port.
</font> */
<font color='#880000'>-
</font> void _CPU_Context_Initialize(
Context_Control *the_context,
uint32_t *stack_base,
<font color='#997700'>@@ -754,7 +1008,7 @@
</font> bool is_fp
);
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This macro is invoked from _Thread_Handler to do whatever CPU
* specific magic is required that must be done in the context of
* the thread when it starts.
<font color='#997700'>@@ -767,13 +1021,12 @@
</font> *
* _Thread_Handler is known to start with SAVE.
*/
<font color='#880000'>-
</font> #define _CPU_Context_Initialization_at_thread_begin() \
do { \
__asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
} while (0)
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This routine is responsible for somehow restarting the currently
* executing task.
*
<font color='#997700'>@@ -781,19 +1034,17 @@
</font> * amount of wrapper code before using the regular restore code in
* of the context switch.
*/
<font color='#880000'>-
</font> #define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * The FP context area for the SPARC is a simple structure and nothing
* special is required to find the "starting load point"
*/
<font color='#880000'>-
</font> #define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This routine initializes the FP context area passed to it to.
*
* The SPARC allows us to use the simple initialization model
<font color='#997700'>@@ -801,7 +1052,6 @@
</font> * at CPU initialization and it is simply copied into the destination
* context.
*/
<font color='#880000'>-
</font> #define _CPU_Context_Initialize_fp( _destination ) \
do { \
*(*(_destination)) = _CPU_Null_fp_context; \
<font color='#997700'>@@ -811,12 +1061,11 @@
</font>
/* Fatal Error manager macros */
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* halts/stops the CPU.
*/
<font color='#880000'>-
</font> #define _CPU_Fatal_halt( _error ) \
do { \
uint32_t level; \
<font color='#997700'>@@ -830,60 +1079,57 @@
</font>
/* Bitfield handler macros */
<font color='#880000'>-/*
- * The SPARC port uses the generic C algorithm for bitfield scan if the
- * CPU model does not have a scan instruction.
- */
-
</font> #if ( SPARC_HAS_BITSCAN == 0 )
<font color='#880000'>-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
</font><font color='#000088'>+ /**
+ * The SPARC port uses the generic C algorithm for bitfield scan if the
+ * CPU model does not have a scan instruction.
+ */
+ #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+ /**
+ * The SPARC port uses the generic C algorithm for bitfield scan if the
+ * CPU model does not have a scan instruction. Thus is needs the generic
+ * data table used by that algorithm.
+ */
+ #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
</font> #else
<font color='#880000'>-#error "scan instruction not currently supported by RTEMS!!"
</font><font color='#000088'>+ #error "scan instruction not currently supported by RTEMS!!"
</font> #endif
/* end of Bitfield handler macros */
<font color='#880000'>-/* Priority handler handler macros */
-
-/*
- * The SPARC port uses the generic C algorithm for bitfield scan if the
- * CPU model does not have a scan instruction.
- */
-
-#if ( SPARC_HAS_BITSCAN == 1 )
-#error "scan instruction not currently supported by RTEMS!!"
-#endif
-
-/* end of Priority handler macros */
-
</font> /* functions */
<font color='#880000'>-/*
- * _CPU_Initialize
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Initialization
</font> *
* This routine performs CPU dependent initialization.
*/
<font color='#880000'>-
</font> void _CPU_Initialize(void);
<font color='#880000'>-/*
- * _CPU_ISR_install_raw_handler
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Raw ISR Installer
</font> *
<font color='#880000'>- * This routine installs new_handler to be directly called from the trap
</font><font color='#000088'>+ * This routine installs @a new_handler to be directly called from the trap
</font> * table.
<font color='#000088'>+ *
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the new ISR handler
+ * @param[in] old_handler will contain the old ISR handler
</font> */
<font color='#880000'>-
</font> void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
<font color='#880000'>-/*
- * _CPU_ISR_install_vector
</font><font color='#000088'>+/**
+ * @brief SPARC Specific RTEMS ISR Installer
</font> *
* This routine installs an interrupt vector.
<font color='#000088'>+ *
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the new ISR handler
+ * @param[in] old_handler will contain the old ISR handler
</font> */
void _CPU_ISR_install_vector(
<font color='#997700'>@@ -892,55 +1138,51 @@
</font> proc_ptr *old_handler
);
<font color='#880000'>-#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
-
-/*
- * _CPU_Thread_Idle_body
- *
- * Some SPARC implementations have low power, sleep, or idle modes. This
- * tries to take advantage of those models.
- */
-
-void *_CPU_Thread_Idle_body( uintptr_t ignored );
-
-#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
-
-/*
- * _CPU_Context_switch
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Context Switch
</font> *
* This routine switches from the run context to the heir context.
<font color='#000088'>+ *
+ * @param[in] run is the currently executing thread
+ * @param[in] heir will become the currently executing thread
</font> */
<font color='#880000'>-
</font> void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
<font color='#880000'>-/*
- * _CPU_Context_restore
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Context Restore
</font> *
* This routine is generally used only to restart self in an
* efficient manner.
<font color='#000088'>+ *
+ * @param[in] new_context is the context to restore
</font> */
<font color='#880000'>-
</font> void _CPU_Context_restore(
Context_Control *new_context
) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
#if defined(RTEMS_SMP)
<font color='#880000'>- /*
- * _CPU_Context_switch_to_first_task_smp
</font><font color='#000088'>+ /**
+ * @brief SPARC Specific Method to Switch to First Task<span style="background-color: #FF0000"> </span>
</font> *
* This routine is only used to switch to the first task on a
* secondary core in an SMP configuration. We do not need to
* flush all the windows and, in fact, this can be dangerous
* as they may or may not be initialized properly.
<font color='#000088'>+ *
+ * @param[in] new_context is the context to restore
</font> */
void _CPU_Context_switch_to_first_task_smp(
Context_Control *new_context
);
<font color='#880000'>- /* address space 1 is uncacheable */
</font><font color='#000088'>+ /**
+ * Macro to access memory and bypass the cache.
+ *
+ * @note address space 1 is uncacheable
+ */
</font> #define SMP_CPU_SWAP( _address, _value, _previous ) \
do { \
register unsigned int _val = _value; \
<font color='#997700'>@@ -953,49 +1195,50 @@
</font> ); \
_previous = _val; \
} while (0)
<font color='#880000'>-
</font> #endif
<font color='#880000'>-/*
- * _CPU_Context_save_fp
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Save FPU Method
</font> *
* This routine saves the floating point context passed to it.
<font color='#000088'>+ *
+ * @param[in] fp_context_ptr is the area to save into
</font> */
<font color='#880000'>-
</font> void _CPU_Context_save_fp(
Context_Control_fp **fp_context_ptr
);
<font color='#880000'>-/*
- * _CPU_Context_restore_fp
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Rstore FPU Method
</font> *
* This routine restores the floating point context passed to it.
<font color='#000088'>+ *
+ * @param[in] fp_context_ptr is the area to restore from
</font> */
<font color='#880000'>-
</font> void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
<font color='#880000'>-
-/*
- * CPU_swap_u32
</font><font color='#000088'>+/**
+ * @brief SPARC Specific Method to Endian Swap an uint32_t<span style="background-color: #FF0000"> </span>
</font> *
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*
<font color='#000088'>+ * @param[in] value is the value to endian swap
+ *
</font> * This version will work on any processor, but if you come across a better
* way for the SPARC PLEASE use it. The most common way to swap a 32-bit
* entity as shown below is not any more efficient on the SPARC.
*
<font color='#880000'>- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
</font><font color='#000088'>+ * - swap least significant two bytes with 16-bit rotate
+ * - swap upper and lower 16-bits
+ * - swap most significant two bytes with 16-bit rotate
</font> *
* It is not obvious how the SPARC can do significantly better than the
* generic code. gcc 2.7.0 only generates about 12 instructions for the
* following code at optimization level four (i.e. -O4).
*/
<font color='#880000'>-
</font> static inline uint32_t CPU_swap_u32(
uint32_t value
)
<font color='#997700'>@@ -1011,6 +1254,13 @@
</font> return( swapped );
}
<font color='#000088'>+/**
+ * @brief SPARC Specific Method to Endian Swap an uint16_t<span style="background-color: #FF0000"> </span>
+ *
+ * The following routine swaps the endian format of a uint16_t.
+ *
+ * @param[in] value is the value to endian swap
+ */
</font> #define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
<font color='#006600'>diff -u rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h:1.16 rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h:1.17
--- rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h:1.16 Mon Apr 18 17:01:39 2011
+++ rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h Tue Jun 21 17:12:10 2011
</font><font color='#997700'>@@ -1,12 +1,15 @@
</font> /**
* @file rtems/score/sparc.h
<font color='#000088'>+ *
+ * This file contains the information required to build
+ * RTEMS for a particular member of the SPARC family. It does
+ * this by setting variables to indicate which implementation
+ * dependent features are present in a particular member
+ * of the family.
</font> */
/*
<font color='#880000'>- * This include file contains information pertaining to the SPARC
- * processor family.
- *
- * COPYRIGHT (c) 1989-1999.
</font><font color='#000088'>+ * COPYRIGHT (c) 1989-2011.
</font> * On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
<font color='#997700'>@@ -24,11 +27,6 @@
</font> #endif
/*
<font color='#880000'>- * This file contains the information required to build
- * RTEMS for a particular member of the "sparc" family. It does
- * this by setting variables to indicate which implementation
- * dependent features are present in a particular member
- * of the family.
</font> *
* Currently recognized feature flags:
*
<font color='#997700'>@@ -45,110 +43,133 @@
</font> * SPARC_PSR_CWP_MASK is derived from this value.
*/
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Some higher end SPARCs have a bitscan instructions. It would
* be nice to take advantage of them. Right now, there is no
* port to a CPU model with this feature and no (untested) code
* that is based on this feature flag.
*/
<font color='#880000'>-
</font> #define SPARC_HAS_BITSCAN 0
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * This should be OK until a port to a higher end SPARC processor
* is made that has more than 8 register windows. If this cannot
* be determined based on multilib settings (v7/v8/v9), then the
* cpu_asm.S code that depends on this will have to move to libcpu.
*/
<font color='#880000'>-
</font> #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
<font color='#880000'>-/*
- * This should be determined based on some soft float derived
- * cpp predefine but gcc does not currently give us that information.
</font><font color='#000088'>+/**
+ * This macro indicates whether this multilib variation has hardware
+ * floating point or not. We use the gcc cpp predefine _SOFT_FLOAT
+ * to determine that.
</font> */
<font color='#880000'>-
-
</font> #if defined(_SOFT_FLOAT)
<font color='#880000'>-#define SPARC_HAS_FPU 0
</font><font color='#000088'>+ #define SPARC_HAS_FPU 0
</font> #else
<font color='#880000'>-#define SPARC_HAS_FPU 1
</font><font color='#000088'>+ #define SPARC_HAS_FPU 1
</font> #endif
<font color='#000088'>+/**
+ * This macro contains a string describing the multilib variant being
+ * build.
+ */
</font> #if SPARC_HAS_FPU
<font color='#880000'>-#define CPU_MODEL_NAME "w/FPU"
</font><font color='#000088'>+ #define CPU_MODEL_NAME "w/FPU"
</font> #else
<font color='#880000'>-#define CPU_MODEL_NAME "w/soft-float"
</font><font color='#000088'>+ #define CPU_MODEL_NAME "w/soft-float"
</font> #endif
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * Define the name of the CPU family.
*/
<font color='#880000'>-
</font> #define CPU_NAME "SPARC"
/*
* Miscellaneous constants
*/
<font color='#880000'>-/*
</font><font color='#000088'>+/**
</font> * PSR masks and starting bit positions
*
<font color='#880000'>- * NOTE: Reserved bits are ignored.
</font><font color='#000088'>+ * @note Reserved bits are ignored.
</font> */
<font color='#880000'>-
</font> #if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
<font color='#880000'>-#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */
</font><font color='#000088'>+ #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */
</font> #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
<font color='#880000'>-#define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */
</font><font color='#000088'>+ #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */
</font> #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
<font color='#880000'>-#define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */
</font><font color='#000088'>+ #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */
</font> #else
<font color='#880000'>-#error "Unsupported number of register windows for this cpu"
</font><font color='#000088'>+ #error "Unsupported number of register windows for this cpu"
</font> #endif
<font color='#000088'>+/** This constant is a mask for the ET bits in the PSR. */
</font> #define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */
<font color='#000088'>+/** This constant is a mask for the PS bits in the PSR. */
</font> #define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */
<font color='#000088'>+/** This constant is a mask for the S bits in the PSR. */
</font> #define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */
<font color='#000088'>+/** This constant is a mask for the PIL bits in the PSR. */
</font> #define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */
<font color='#000088'>+/** This constant is a mask for the EF bits in the PSR. */
</font> #define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */
<font color='#000088'>+/** This constant is a mask for the EC bits in the PSR. */
</font> #define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */
<font color='#000088'>+/** This constant is a mask for the ICC bits in the PSR. */
</font> #define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */
<font color='#000088'>+/** This constant is a mask for the VER bits in the PSR. */
</font> #define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */
<font color='#000088'>+/** This constant is a mask for the IMPL bits in the PSR. */
</font> #define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */
<font color='#000088'>+/** This constant is the starting bit position of the CWP in the PSR. */
</font> #define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */
<font color='#000088'>+/** This constant is the starting bit position of the ET in the PSR. */
</font> #define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */
<font color='#000088'>+/** This constant is the starting bit position of the PS in the PSR. */
</font> #define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */
<font color='#000088'>+/** This constant is the starting bit position of the S in the PSR. */
</font> #define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */
<font color='#000088'>+/** This constant is the starting bit position of the PIL in the PSR. */
</font> #define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */
<font color='#000088'>+/** This constant is the starting bit position of the EF in the PSR. */
</font> #define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */
<font color='#000088'>+/** This constant is the starting bit position of the EC in the PSR. */
</font> #define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */
<font color='#000088'>+/** This constant is the starting bit position of the ICC in the PSR. */
</font> #define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */
<font color='#000088'>+/** This constant is the starting bit position of the VER in the PSR. */
</font> #define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */
<font color='#000088'>+/** This constant is the starting bit position of the IMPL in the PSR. */
</font> #define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
#ifndef ASM
<font color='#880000'>-/*
- * Standard nop
</font><font color='#000088'>+/**
+ * This macro is a standard nop instruction.
</font> */
<font color='#880000'>-
</font> #define nop() \
do { \
__asm__ volatile ( "nop" ); \
} while ( 0 )
<font color='#880000'>-/*
- * Get and set the PSR
</font><font color='#000088'>+/**
+ * @brief Macro to Obtain the PSR
+ *
+ * This macro returns the current contents of the PSR register in @a _psr.
</font> */
<font color='#880000'>-
</font> #define sparc_get_psr( _psr ) \
do { \
(_psr) = 0; \
__asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
} while ( 0 )
<font color='#000088'>+/**
+ * @brief Macro to Set the PSR
+ *
+ * This macro sets the PSR register to the value in @a _psr.
+ */
</font> #define sparc_set_psr( _psr ) \
do { \
__asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
<font color='#997700'>@@ -157,30 +178,42 @@
</font> nop(); \
} while ( 0 )
<font color='#880000'>-/*
- * Get and set the TBR
</font><font color='#000088'>+/**
+ * @brief Macro to Obtain the TBR
+ *
+ * This macro returns the current contents of the TBR register in @a _tbr.
</font> */
<font color='#880000'>-
</font> #define sparc_get_tbr( _tbr ) \
do { \
(_tbr) = 0; /* to avoid unitialized warnings */ \
__asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
<font color='#000088'>+/**
+ * @brief Macro to Set the TBR
+ *
+ * This macro sets the TBR register to the value in @a _tbr.
+ */
</font> #define sparc_set_tbr( _tbr ) \
do { \
__asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
<font color='#880000'>-/*
- * Get and set the WIM
</font><font color='#000088'>+/**
+ * @brief Macro to Obtain the WIM
+ *
+ * This macro returns the current contents of the WIM field in @a _wim.
</font> */
<font color='#880000'>-
</font> #define sparc_get_wim( _wim ) \
do { \
__asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
} while ( 0 )
<font color='#000088'>+/**
+ * @brief Macro to Set the WIM
+ *
+ * This macro sets the WIM field to the value in @a _wim.
+ */
</font> #define sparc_set_wim( _wim ) \
do { \
__asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \
<font color='#997700'>@@ -189,33 +222,64 @@
</font> nop(); \
} while ( 0 )
<font color='#880000'>-/*
- * Get and set the Y
</font><font color='#000088'>+/**
+ * @brief Macro to Obtain the Y Register
+ *
+ * This macro returns the current contents of the Y register in @a _y.
</font> */
<font color='#880000'>-
</font> #define sparc_get_y( _y ) \
do { \
__asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
<font color='#000088'>+/**
+ * @brief Macro to Set the Y Register
+ *
+ * This macro sets the Y register to the value in @a _y.
+ */
</font> #define sparc_set_y( _y ) \
do { \
__asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
<font color='#880000'>-/*
- * Manipulate the interrupt level in the psr
</font><font color='#000088'>+/**
+ * @brief SPARC Disable Processor Interrupts
+ *
+ * This method is invoked to disable all maskable interrupts.
+ *
+ * @return This method returns the entire PSR contents.
</font> */
<font color='#880000'>-
</font> uint32_t sparc_disable_interrupts(void);
<font color='#880000'>-void sparc_enable_interrupts(uint32_t);
</font>
<font color='#880000'>-#define sparc_flash_interrupts( _level ) \
</font><font color='#000088'>+/**
+ * @brief SPARC Enable Processor Interrupts
+ *
+ * This method is invoked to enable all maskable interrupts.
+ *
+ * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
+ */
+void sparc_enable_interrupts(uint32_t psr);
+
+/**
+ * @brief SPARC Flash Processor Interrupts
+ *
+ * This method is invoked to temporarily enable all maskable interrupts.
+ *
+ * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
+ */
+#define sparc_flash_interrupts( _psr ) \
</font> do { \
<font color='#880000'>- sparc_enable_interrupts( (_level) ); \
- _level = sparc_disable_interrupts(); \
</font><font color='#000088'>+ sparc_enable_interrupts( (_psr) ); \
+ _psr = sparc_disable_interrupts(); \
</font> } while ( 0 )
<font color='#000088'>+/**
+ * @brief SPARC Obtain Interrupt Level
+ *
+ * This method is invoked to obtain the current interrupt disable level.
+ *
+ * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
+ */
</font> #define sparc_get_interrupt_level( _level ) \
do { \
register uint32_t _psr_level = 0; \
<font color='#006600'>diff -u rtems/cpukit/score/cpu/sparc/rtems/score/types.h:1.18 rtems/cpukit/score/cpu/sparc/rtems/score/types.h:1.19
--- rtems/cpukit/score/cpu/sparc/rtems/score/types.h:1.18 Thu Jul 29 12:51:58 2010
+++ rtems/cpukit/score/cpu/sparc/rtems/score/types.h Tue Jun 21 17:12:10 2011
</font><font color='#997700'>@@ -1,12 +1,12 @@
</font> /**
* @file rtems/score/types.h
<font color='#000088'>+ *
+ * This include file contains type definitions pertaining to the
+ * SPARC processor family.
</font> */
/*
<font color='#880000'>- * This include file contains type definitions pertaining to the
- * SPARC processor family.
- *
- * COPYRIGHT (c) 1989-1999.
</font><font color='#000088'>+ * COPYRIGHT (c) 1989-2011.
</font> * On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
<font color='#997700'>@@ -27,12 +27,27 @@
</font> extern "C" {
#endif
<font color='#880000'>-/*
- * This section defines the basic types for this processor.
</font><font color='#000088'>+/**
+ * @brief Priority Bit Map Type
+ *
+ * On the SPARC, there is no bitscan instruction and no penalty associated
+ * for using 16-bit variables. With no overriding architectural factors,
+ * just using a uint16_t.
</font> */
<font color='#000088'>+typedef uint16_t Priority_bit_map_Control;
</font>
<font color='#880000'>-typedef uint16_t Priority_bit_map_Control;
</font><font color='#000088'>+/**
+ * @brief SPARC ISR Handler Return Type
+ *
+ * This is the type which SPARC ISR Handlers return.
+ */
</font> typedef void sparc_isr;
<font color='#000088'>+
+/**
+ * @brief SPARC ISR Handler Prototype
+ *
+ * This is the prototype for SPARC ISR Handlers.
+ */
</font> typedef void ( *sparc_isr_entry )( void );
#ifdef __cplusplus
</pre>
<p> </p>
<p>--<br />
<small>Generated by <a href="http://www.codewiz.org/projects/index.html#loginfo">Deluxe Loginfo</a> 2.122 by Bernardo Innocenti <bernie@develer.com></small></p>
</body>
</html>