<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>change log for rtems (2011-07-28)</title>
</head>
<body text='#000000' bgcolor='#ffffff'>
<a name='cs1'></a>
<table border='0' cellspacing='0' cellpadding='5' width='100%' bgcolor='#eeeeee'>
<tr><td colspan='3' bgcolor='#dddddd'>
<font color='#bb2222'><strong>jennifer</strong></font>
</td></tr>
<tr><td colspan='3' bgcolor='#dddddd'><pre>2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1801
* shared/irq_asm.S: Modifications to synch the sparc with the smp
working tree.
</pre></td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/c/src/lib/libbsp/sparc/ChangeLog.diff?r1=text&tr1=1.87&r2=text&tr2=1.88&diff_format=h">M</a></td><td width='1%'>1.88</td><td width='100%'>c/src/lib/libbsp/sparc/ChangeLog</td></tr>
<tr><td width='1%'><a href="http://www.rtems.com/cgi-bin/viewcvs.cgi//rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S.diff?r1=text&tr1=1.1&r2=text&tr2=1.2&diff_format=h">M</a></td><td width='1%'>1.2</td><td width='100%'>c/src/lib/libbsp/sparc/shared/irq_asm.S</td></tr>
</table>
<pre>
<font color='#006600'>diff -u rtems/c/src/lib/libbsp/sparc/ChangeLog:1.87 rtems/c/src/lib/libbsp/sparc/ChangeLog:1.88
--- rtems/c/src/lib/libbsp/sparc/ChangeLog:1.87 Tue Jun 28 15:29:33 2011
+++ rtems/c/src/lib/libbsp/sparc/ChangeLog Thu Jul 28 12:33:07 2011
</font><font color='#997700'>@@ -1,3 +1,9 @@
</font><font color='#000088'>+2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+ PR 1801
+ * shared/irq_asm.S: Modifications to synch the sparc with the smp
+ working tree.
+
</font> 2011-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
Jennifer Averett <jennifer.averett@OARcorp.com>
<font color='#006600'>diff -u rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S:1.1 rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S:1.2
--- rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S:1.1 Wed Mar 16 15:05:30 2011
+++ rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S Thu Jul 28 12:33:07 2011
</font><font color='#997700'>@@ -164,69 +164,6 @@
</font> mov %sp, %o1 ! 2nd arg to ISR Handler
/*
<font color='#880000'>- * Increment ISR nest level and Thread dispatch disable level.
- *
- * Register usage for this section:
- *
- * l4 = _Thread_Dispatch_disable_level pointer
- * l5 = _ISR_Nest_level pointer
- * l6 = _Thread_Dispatch_disable_level value
- * l7 = _ISR_Nest_level value
- *
- * NOTE: It is assumed that l4 - l7 will be preserved until the ISR
- * nest and thread dispatch disable levels are unnested.
- */
-
- sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4
- ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
-
- PUBLIC(_ISR_PER_CPU)
-SYM(_ISR_PER_CPU):
-#if defined(RTEMS_SMP)
- sethi %hi(_Per_CPU_Information_p), %l5
- add %l5, %lo(_Per_CPU_Information_p), %l5
- #if BSP_LEON3_SMP<span style="background-color: #FF0000"> </span>
- /* LEON3 SMP support */
- rd %asr17, %l7
- srl %l7, 28, %l7 /* CPU number is upper 4 bits so shift */
- sll %l7, 2, %l7 /* l7 = offset */
- add %l5, %l7, %l5
- #endif
- ld [%l5], %l5 /* l5 = pointer to per CPU */
- nop
- nop
-#else
- sethi %hi(_Per_CPU_Information), %l5
- add %l5, %lo(_Per_CPU_Information), %l5
-#endif
- ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
-
- add %l6, 1, %l6
- st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
-
- add %l7, 1, %l7
- st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
-
- /*
- * If ISR nest level was zero (now 1), then switch stack.
- */
-
- mov %sp, %fp
- subcc %l7, 1, %l7 ! outermost interrupt handler?
- bnz dont_switch_stacks ! No, then do not switch stacks
-
- ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
-
-dont_switch_stacks:
- /*
- * Make sure we have a place on the stack for the window overflow
- * trap handler to write into. At this point it is safe to
- * enable traps again.
- */
-
- sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
-
- /*
</font> * Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
* set the PIL in the %psr to mask off interrupts with lower priority.
* The original %psr in %l0 is not modified since it will be restored
<font color='#997700'>@@ -316,6 +253,86 @@
</font> wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
dont_fix_pil2:
<font color='#000088'>+ PUBLIC(_ISR_PER_CPU)
+SYM(_ISR_PER_CPU):
+
+#if defined(RTEMS_SMP)
+ sethi %hi(_Per_CPU_Information_p), %l5
+ add %l5, %lo(_Per_CPU_Information_p), %l5
+ #if BSP_LEON3_SMP<span style="background-color: #FF0000"> </span>
+ /* LEON3 SMP support */
+ rd %asr17, %l7
+ srl %l7, 28, %l7 /* CPU number is upper 4 bits so shift */
+ sll %l7, 2, %l7 /* l7 = offset */
+ add %l5, %l7, %l5
+ #endif
+ ld [%l5], %l5 /* l5 = pointer to per CPU */
+ nop
+ nop
+
+ /*
+ * On multi-core system, we need to use SMP safe versions
+ * of ISR and Thread Dispatch critical sections.
+ *
+ * _ISR_SMP_Enter returns the interrupt nest level. If we are
+ * outermost interrupt, then we need to switch stacks.
+ */
+ mov %sp, %fp
+ call SYM(_ISR_SMP_Enter), 0
+ nop ! delay slot
+ cmp %o0, 0
+#else
+ /*
+ * On single core system, we can directly use variables.
+ *
+ * Increment ISR nest level and Thread dispatch disable level.
+ *
+ * Register usage for this section:
+ *
+ * l4 = _Thread_Dispatch_disable_level pointer
+ * l5 = _ISR_Nest_level pointer
+ * l6 = _Thread_Dispatch_disable_level value
+ * l7 = _ISR_Nest_level value
+ *
+ * NOTE: It is assumed that l4 - l7 will be preserved until the ISR
+ * nest and thread dispatch disable levels are unnested.
+ */
+ sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4
+ ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
+
+ sethi %hi(_Per_CPU_Information), %l5
+ add %l5, %lo(_Per_CPU_Information), %l5
+
+ ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
+
+ add %l6, 1, %l6
+ st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
+
+ add %l7, 1, %l7
+ st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
+
+ /*
+ * If ISR nest level was zero (now 1), then switch stack.
+ */
+ mov %sp, %fp
+ subcc %l7, 1, %l7 ! outermost interrupt handler?
+#endif
+
+ /*
+ * Do we need to switch to the interrupt stack?
+ */
+ bnz dont_switch_stacks ! No, then do not switch stacks
+ ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
+
+dont_switch_stacks:
+ /*
+ * Make sure we have a place on the stack for the window overflow
+ * trap handler to write into. At this point it is safe to
+ * enable traps again.
+ */
+
+ sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+
</font> /*
* Vector to user's handler.
*
<font color='#997700'>@@ -336,6 +353,17 @@
</font> call %g4, 0
nop ! delay slot
<font color='#000088'>+#if defined(RTEMS_SMP)
+ call SYM(_ISR_SMP_Exit), 0
+ nop ! delay slot
+ cmp %o0, 0
+ bz simple_return
+#else
+ !sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4
+ !ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
+ !ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
+#endif
+
</font> /*
* Redisable traps so we can finish up the interrupt processing.
* This is a VERY conservative place to do this.
<font color='#997700'>@@ -346,6 +374,7 @@
</font> mov %l0, %psr ! **** DISABLE TRAPS ****
nop; nop; nop
<font color='#000088'>+#if !defined(RTEMS_SMP)
</font> /*
* Decrement ISR nest level and Thread dispatch disable level.
*
<font color='#997700'>@@ -389,7 +418,7 @@
</font>
orcc %l5, %g0, %g0 ! Is thread switch necessary?
bz simple_return ! No, then return
<font color='#880000'>-
</font><font color='#000088'>+#endif
</font> /*
* Invoke interrupt dispatcher.
*/
</pre>
<p> </p>
<p>--<br />
<small>Generated by <a href="http://www.codewiz.org/projects/index.html#loginfo">Deluxe Loginfo</a> 2.122 by Bernardo Innocenti <bernie@develer.com></small></p>
</body>
</html>