[Bug 1607] __RTEMS_SIZEOF_VOID_P__ flawed design

bugzilla-daemon at rtems.org bugzilla-daemon at rtems.org
Mon Jul 12 20:09:34 UTC 2010


https://www.rtems.org/bugzilla/show_bug.cgi?id=1607

--- Comment #10 from Gedare <giddyup44 at yahoo.com> 2010-07-12 15:09:32 CDT ---
(In reply to comment #9)
> (In reply to comment #8)
> > (In reply to comment #7)
> > > (In reply to comment #6)
> > > > 1. We need this per CPU structure to support multi-core systems.
> > > > 2. We have to access fields of this CPU structure in assembly code.
> > > Not quite - Your design does not allow otherwise.
> > > 
> > > You could redesign your code in such a way it doesn't have these
> > > limitations/restriction attached, e.g. 
> > > * by rewriting your code in inline-asm (There you can utilize sizeof())
> > 
> > Inline-asm has be be within a function body? 
> Yes, but there are ways to work around this.
> 
> E.g. one trick is to wrap everything into one C-function and to add functions
> entries using inline-asm inside of it.
> 
This seems like a pretty "dirty" hack to me, but worth considering. Note that
this would involve rewriting all platforms' interrupt handling code as C and
inline assembly rather than the current .S files.  However, this solutions
allows for the compiler to generate constants and remains as efficient as the
current autoconf-based solution.

> > > or
> > > * by using helper const variables being set up in C and refer to them in asm or
> > > inline-asm
> > 
> > This is a performance penalty in a time critical section.
> Only marginally. The benefit: it's better portable.
> 
I had this thought, it does incur some small amount of storage and an extra
memory reference everytime the assembly code needs to re-load the
sizeof(void*), but as Ralf points out this is a small overhead -- as long as
the value does not need to be loaded too many times by ISR handler.  Since only
one variable is required by the percpu code (for the sizeof(void*)), it might
be sensible to place such a variable at the start of the Per_CPU_Control
structure. This again requires additions to every platform's interrupt handling
code.

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