[Bug 1573] Per CPU Patch -- SMP Step #1

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=1573

Sebastian Huber <sebastian.huber at embedded-brains.de> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |REOPENED
         Resolution|FIXED                       |

--- Comment #18 from Sebastian Huber <sebastian.huber at embedded-brains.de> 2010-07-20 03:43:39 CDT ---
We should change the Per_CPU_Control structure to this:

typedef struct {
  int isr_nest_level;
  bool dispatch_needed;
  Thread_Control *executing;
  Thread_Control *heir;
  Thread_Control *idle;
  #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) \
    || (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    void *interrupt_stack_low;
    void *interrupt_stack_high;
  #endif
} Per_CPU_Control;

1. There is no need to use uint32_t for the isr_nest_level.  We should use the
natural register value of the architecture.

2. The volatile qualifier is not needed in dispatch_needed.  See also

http://www.mjmwired.net/kernel/Documentation/volatile-considered-harmful.txt

3. Optional fields should be at the end of the structure.

4. Moving the assembler code relevant fields to the structure begin simplifies
the offset value determination.  Relevant for the assembler code are
isr_nest_level and dispatch_needed.  The offset to isr_nest_level is trivial. 
The offset to dispatch_needed is determined by sizeof(int) on nearly all
targets.  Does someone know a counter example?

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