[Bug 1946] Asymmetric SMP mega-patch

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=1946

Sebastian Huber <sebastian.huber at embedded-brains.de> changed:

           What    |Removed                     |Added
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                 CC|                            |sebastian.huber at embedded-br
                   |                            |ains.de

--- Comment #4 from Sebastian Huber <sebastian.huber at embedded-brains.de> 2011-10-27 05:25:22 CDT ---
(In reply to comment #3)
[...]
>  - The architecture on which we are running in AMP configuration is indeed
> called k1. Of course, we will remove all references to it. One reason why we
> have such specific parts is that our low-level lock instructions did not fit
> the SMP_CPU_SWAP macro and general RTEMS lock mechanism, which made too many
> assumptions (32 bit lock value, for example). We will clean that up.
[...]

Better would be to clean the SMP_CPU_SWAP macro and general RTEMS lock
mechanism up.

On FreeBSD an uintptr_t is used instead of the uint32_t, maybe we should even
make it architecture dependent.

ISR_Level _SMP_lock_spinlock_simple_Obtain(
  SMP_lock_spinlock_simple_Control *lock
)
{
   ISR_Level  level = 0;
   uint32_t   value = 1;
   uint32_t   previous;

   /* Note: Disable provides an implicit memory barrier. */
  _ISR_Disable_on_this_core( level );
   do {
     RTEMS_COMPILER_MEMORY_BARRIER();
     SMP_CPU_SWAP( lock, value, previous );
     RTEMS_COMPILER_MEMORY_BARRIER();
   } while (previous == 1);

  return level;
}

Here we disable the interrupts and then spin around.  This is very bad.  We
should flash the interrupts before a retry.  This is what I used for the QorIQ:

    .global qoriq_spin_lock
    .global qoriq_spin_unlock

qoriq_spin_lock:
    li    r0, 1
    mfmsr    r4
    GET_INTERRUPT_MASK r5
    andc    r5, r4, r5
    b    2f
1:
    mtmsr    r4
2:
    lwarx    r6, r0, r3
    cmpwi    r6, 0
    bne    2b
    mtmsr    r5
    stwcx.    r0, r0, r3
    bne    1b
    isync
    mr    r3, r4
    blr

qoriq_spin_unlock:
    msync
    li    r0, 0
    stw    r0, 0(r3)
    mtmsr    r4
    blr

You have to account also for architecture dependent memory synchronization,
e.g. the msync and isync in this PowerPC example.  A
RTEMS_COMPILER_MEMORY_BARRIER() is not enough.

In general we lack atomic primitives:

https://www.rtems.org/bugzilla/show_bug.cgi?id=1455

Instead of inventing the wheel again, we should use the stuff provided by the
latest C++ standard:

http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2145.html

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