[Bug 2003] Instruction cache problem in gen5200 bsps

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=2003

--- Comment #8 from Sebastian Huber <sebastian.huber at embedded-brains.de> 2012-02-06 02:32:14 CST ---
The current setting is a bit coarse.  The BSP sets HID0[ICE].  This means the
instruction cache is available.  Since we do not set the MSR[IR] bit, we use
the default memory attributes (IBAT and MMU settings are ignored).  By default
the cache is on.  See e300 core manual section
4.4.1 "Memory/Cache Access Attributes (WIMG Bits)".  We can of coarse enhance
the BSP startup to set also the IBAT registers.

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