[Bug 2003] New: Instruction cache problem in gen5200 bsps

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=2003

           Summary: Instruction cache problem in gen5200 bsps
           Product: RTEMS
           Version: 4.10
          Platform: powerpc
        OS/Version: RTEMS
            Status: NEW
          Severity: major
          Priority: P3
         Component: bsps
        AssignedTo: joel.sherrill at oarcorp.com
        ReportedBy: ktaylan at gmail.com


There is a function called "cpu_init" in gen5200 bsp. In that function there is
a code segment that enables instruction cache. However without settings BATs
for instruction cache and settings some bits in HID0 register, instruction
cache cannot be enabled. The only code that enables instruction cache in
current function is;

msr = ppc_machine_state_register();

msr |= MSR_IR;

ppc_set_machine_state_register(msr);

But additionally the below code should be added and BATs for instruction cache
should be set. In the attachment there is a code for updated cpuinit.c file.
This is done for Phytec MPC5200B I/O CPU module (which is not defined in
current bsp list. I hope i will propose to add this bsp codes to upcoming
releases)

PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICE | HID0_ICFI);
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICFI);

NOTE: Without enabling instruction cache performance drops 4-5 times.

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