[Bug 2004] New: sparc64: problem using softint and timer together

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=2004

           Summary: sparc64: problem using softint and timer together
           Product: RTEMS
           Version: HEAD
          Platform: sparc64
        OS/Version: RTEMS
            Status: NEW
          Severity: normal
          Priority: P3
         Component: bsps
        AssignedTo: joel.sherrill at oarcorp.com
        ReportedBy: gedare at rtems.org


Created attachment 1408
  --> https://www.rtems.org/bugzilla/attachment.cgi?id=1408
new assembly macros for writing to softint register

sparc64 hardware shares an interrupt level (14) between tick comparison and
software-raised  interrupts. current bsps do not handle the situation of both
interrupt sources simultaneously, so software interrupts cannot be used when
the timer also is used.  What happens is the interrupt level (PIL) does not get
set/reset properly and interrupts are missed.

The attached patch is a work-around that hacks the clock isr, but I need to
look more closely at the generic ISR handling code to see if the bug is due to
interactions between PIL assignment, interrupt enable/disable, and scheduling.

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