[Bug 2003] Instruction cache problem in gen5200 bsps

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=2003

--- Comment #7 from ktaylan at gmail.com 2012-02-02 03:07:41 CST ---
We have compared the performance of rtems using gcc by executing same assembly
instruction with our native system. During that we faced up with 4-5 times
performance drop. So after that we analyzed and we found the problem as i
described. If we disable HID0 register bits settings related with instruction
cache we are easily seeing performance drop. e300 core manual says that MSR_IR
bit enables or disables address translation but does not enable cache. In order
to enable instruction cache the only thing is to set ICE bit in HID0. By the
way we don't know is there any other settings or functions that enable or
disable instruction cache. May be we are omitting some things.

-- 
Configure bugmail: https://www.rtems.org/bugzilla/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are watching all bug changes.