[RTEMS Project] #1740: Change PowerPC multi-libs for e200 and e500 cores

[RTEMS trac]

#1740: Change PowerPC multi-libs for e200 and e500 cores
-----------------------------+-----------------------------
 Reporter:  sebastian.huber  |       Owner:  ralf.corsepius
     Type:  defect           |      Status:  closed
 Priority:  normal           |   Milestone:  4.11
Component:  GCC              |     Version:  4.11
 Severity:  normal           |  Resolution:  fixed
 Keywords:                   |
-----------------------------+-----------------------------
Changes (by gedare):

 * version:  unspecified => 4.11
 * milestone:   => 4.11


Old description:

> Some e200, the e500, and the e500v2 cores have a SPE and embedded
> floating point unit.  They use the general purpose registers for floating
> point operations.  Three multi-lib variants are useful here:
>
>  1. Software floating point
>  2. 32-bit hardware floating point (e200 and e500)
>  3. 64-bit hardware floating point (e500v2)
>
> We should not support SPE multi-lib variants, because this may effect the
> interrupt context save and restore overhead.  There is also an open GCC
> bug related to the SPE: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47751
>
> The patch is based on 'contrib/crossrpms/patches/gcc-
> core-4.5.2-rtems4.11-20101216.diff'.
>
> One question to a part of it in t-rtems:
>
> @@ -47,6 +47,10 @@ MULTILIB_MATCHES     += mcpu?7400=mcpu?7450
>  # Map 750 to .
>  MULTILIB_MATCHES       += mcpu?750=
>
> +# Map e500, 8548 to 8540
> +MULTILIB_MATCHES       += mcpu?8540=mcpu?e500
> +MULTILIB_MATCHES       += mcpu?8540=mcpu?8548
> +
>  # Soft-float only, default implies msoft-float
>  # NOTE: Must match with MULTILIB_MATCHES_FLOAT and MULTILIB_MATCHES
>  MULTILIB_SOFTFLOAT_ONLY = \
>
> Why do we need this?  For example a -mcpu=e500 yields a 'cc1: error: bad
> value (e500) for -mcpu= switch'.
>
> Also in rtems.h:
>
> +%{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540}  } }"
>
> This will not trigger in case of -mcpu=8548.

New description:

 Some e200, the e500, and the e500v2 cores have a SPE and embedded floating
 point unit.  They use the general purpose registers for floating point
 operations.  Three multi-lib variants are useful here:

  1. Software floating point
  2. 32-bit hardware floating point (e200 and e500)
  3. 64-bit hardware floating point (e500v2)

 We should not support SPE multi-lib variants, because this may effect the
 interrupt context save and restore overhead.  There is also an open GCC
 bug related to the SPE: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47751

 The patch is based on 'contrib/crossrpms/patches/gcc-
 core-4.5.2-rtems4.11-20101216.diff'.

 One question to a part of it in t-rtems:

 @@ -47,6 +47,10 @@ MULTILIB_MATCHES     += mcpu?7400=mcpu?7450
  # Map 750 to .
  MULTILIB_MATCHES       += mcpu?750=

 +# Map e500, 8548 to 8540
 +MULTILIB_MATCHES       += mcpu?8540=mcpu?e500
 +MULTILIB_MATCHES       += mcpu?8540=mcpu?8548
 +
  # Soft-float only, default implies msoft-float
  # NOTE: Must match with MULTILIB_MATCHES_FLOAT and MULTILIB_MATCHES
  MULTILIB_SOFTFLOAT_ONLY = \

 Why do we need this?  For example a -mcpu=e500 yields a 'cc1: error: bad
 value (e500) for -mcpu= switch'.

 Also in rtems.h:

 +%{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540}  } }"

 This will not trigger in case of -mcpu=8548.

--

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Ticket URL: <http://devel.rtems.org/ticket/1740#comment:14>
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RTEMS Project