[RTEMS Project] #2369: [PowerPC Book E] Invalid mftb instruction in _CPU_Counter_read()
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trac at rtems.org
Thu Jul 9 06:22:58 UTC 2015
#2369: [PowerPC Book E] Invalid mftb instruction in _CPU_Counter_read()
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Reporter: nick.withers | Owner:
Type: defect | Status: new
Priority: normal | Milestone: 4.11.1
Component: General | Version: 4.11
Severity: normal | Resolution:
Keywords: |
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Comment (by sebastian.huber):
A BSP for the e500 should use the "-mcpu=8540 -meabi -msdata=sysv -fno-
common" options.
I am not sure if the SPR 268 exists really on all PowerPCs supported by
RTEMS:
static inline uint64_t PPC_Get_timebase_register( void )
{
uint32_t tbr_low;
uint32_t tbr_high;
uint32_t tbr_high_old;
uint64_t tbr;
do {
#if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
/* See comment above (CPU_Get_timebase_low) */
__asm__ volatile( "mftbu %0" : "=r" (tbr_high_old));
__asm__ volatile( "mftb %0" : "=r" (tbr_low));
__asm__ volatile( "mftbu %0" : "=r" (tbr_high));
#else
__asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
__asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low));
__asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high));
#endif
} while ( tbr_high_old != tbr_high );
tbr = tbr_high;
tbr <<= 32;
tbr |= tbr_low;
return tbr;
}
However these exceptions look more like museum hardware.
--
Ticket URL: <http://devel.rtems.org/ticket/2369#comment:3>
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