[RTEMS Project] #2270: SPARC: Optimized floating-point context handling

[RTEMS trac]

#2270: SPARC: Optimized floating-point context handling
-----------------------------+------------------------------
 Reporter:  sebastian.huber  |       Owner:  sebastian.huber
     Type:  enhancement      |      Status:  accepted
 Priority:  normal           |   Milestone:  4.11.1
Component:  cpukit           |     Version:  4.11
 Severity:  normal           |  Resolution:
 Keywords:  SPARC            |
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Comment (by sebastian.huber):

 From the SPARC Architecture Manual Version 8 we have:

 "PSR_enable_floating-point (EF)

 Bit 12 determines whether the FPU is enabled. If disabled, a floating-
 point
 instruction will trap. 1 = enabled, 0 = disabled. If an implementation
 does not
 support a hardware FPU, PSR.EF should always read as 0 and writes to it
 should
 be ignored.

 Programming Note

 Software can use the EF and EC bits to determine whether a particular
 process uses the FPU or CP.
 If a process does not use the FPU/CP, its registers do not need to be
 saved across a context switch."

 Where is it documented that the PSR[EF] may have side-effects like a
 power-down mode or leads to a pause of FP instructions?  Do the LEON
 processors such things?  Is an interrupt not context synchronizing on
 SPARC (like PowerPC for example)?

 The PSR[EF] is only set in case SPARC_HAS_FPU == 1 and the thread has the
 FP attribute.  So we already touch this bit during a context switch.  Why
 are the interrupts different?

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Ticket URL: <http://devel.rtems.org/ticket/2270#comment:10>
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