[RTEMS Project] #2343: [Patch] Fix Zynq SMP boot

[RTEMS trac]

#2343: [Patch] Fix Zynq SMP boot
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 Reporter:  jbrandmeyer                 |       Owner:
     Type:  defect                      |      Status:  new
 Priority:  high                        |   Milestone:  4.11.1
Component:  SMP                         |     Version:  4.10
 Severity:  normal                      |  Resolution:
 Keywords:  zynq, xilinx_zynq_zedboard  |
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Comment (by jbrandmeyer):

 What it really needs is for the write to be observable by the other CPU.
 In order to make that happen, it needs to be device memory because of a
 confluence of issues:

 * RTEMS initializes the MMU and caches before starting up other CPUs.
 * The other CPU does not have its MMU enabled in its waiting-to-startup
 state.
 * Normal memory is cachable.
 * RTEMS does not support cache flush functions in ARMv7-A, only ARMv5TEJ
 (see c/src/lib/libcpu/arm/shared/include/cache_.h)

 So, marking the memory as 'device' memory seemed like the safest way
 around those issues.

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Ticket URL: <http://devel.rtems.org/ticket/2343#comment:3>
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