[RTEMS Project] #2460: arm-gic.h - GIC_ID_TO_TWO_BITS_REG_OFFSET(id) incorrectly defined

[RTEMS trac]

#2460: arm-gic.h - GIC_ID_TO_TWO_BITS_REG_OFFSET(id) incorrectly defined
----------------------+--------------------
 Reporter:  budhe888  |      Owner:
     Type:  defect    |     Status:  new
 Priority:  normal    |  Milestone:  4.11.1
Component:  bsps      |    Version:  4.11
 Severity:  normal    |   Keywords:
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 This bug pertains to the ARM Generic Interrupt Controller (GIC) register
 utility functions in

 {{{c/src/lib/libbsp/arm/shared/include/arm-gic.h}}}

 The following routines all use the macro
 {{{GIC_ID_TO_TWO_BITS_REG_OFFSET(id)}}}:

 {{{
 gic_id_get_handling_mode
 gic_id_set_handling_mode
 gic_id_get_trigger_mode
 gic_id_set_trigger_mode
 }}}

 These routines set the {{{GIC_ICFGRn}}} set of registers. These registers
 have 2-bit bit fields. Let's take the trigger mode routines as an example
 of the bug, but it applies to the handling mode as well. The GIC
 specification from ARM states that for a particular interrupt ID ''m'' the
 register ''n'' and bit field ''F'' is found by:

 ''n = m DIV 16''
 ''F = m MOD 16''

 And the bit location in register ''n'' is defined as ''[2F+1:2F]''.
 However, the macro  {{{GIC_ID_TO_TWO_BITS_REG_OFFSET(id)}}} and the
 routines that use it, set bits ''[F+1:F]''.

 I have tested this by using the set_trigger_mode routine to set an
 interrupt to be edge triggered, but the correct bit does not get set, and
 the interrupt still behaves in a level triggered fashion. When I adjust
 the macro to have a {{{<< 1}}} it works correctly.

 If someone can verify my logic at least, then I can submit a tested patch.

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Ticket URL: <http://devel.rtems.org/ticket/2460>
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