[RTEMS Project] #2438: ARM cache problem after libdl load

[RTEMS trac]

#2438: ARM cache problem after libdl load
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 Reporter:  pggauvin  |      Owner:  chrisj
     Type:  defect    |     Status:  new
 Priority:  normal    |  Milestone:  4.11.1
Component:  libdl     |    Version:  4.11
 Severity:  normal    |   Keywords:  libdl, ARM, ZedBoard, Zynq
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 * '''RTEMS Version:''' Branch "4.11", commit
 edf77328c1813e15a293841dd33995fb11bd4bec
 * '''System type:''' ARM Cortex-A9, Xilinx Zynq 7020, xilinx_zynq_zedboard
 BSP
 * '''Compiler toolchain version:''' GCC 4.9.3, Newlib 2.2.0.20150423,
 Binutils 2.24
 * '''RTEMS configure options:''' {{{ --target=arm-rtems4.11 --enable-
 rtemsbsp="xilinx_zynq_a9_qemu xilinx_zynq_zedboard"  --enable-posix
 --prefix=$HOME/development/rtems/4.11 --enable-tests }}}
 * '''Code used to reproduce:'''
 [https://github.com/RTEMS/rtems/tree/4.11/testsuites/libtests/dl01
 testsuites/libtests/dl01]

 '''Expected Behavior'''

 Successful execution of the loaded function from dl-o1.o. Note that the
 dl01 example runs successfully in QEMU with the xilinx_zynq_a9_qemu BSP.

 '''Actual Behavior'''

 System crash on execution of loaded code. After the first branch is taken
 to loaded code (dl-load.c:54), GDB indicates that the processor is
 executing instructions at the correct address, but they do not behave as
 expected, eventually leading to the system rebooting.

 After discussion on the users mailing list, it was found that flushing the
 data cache and invalidating the instruction cache before calling the
 loaded function resulted in its successful execution. This was tested by
 adding the following at dl-load.c:54:

 {{{
 rtems_cache_flush_entire_data();
 rtems_cache_invalidate_entire_instruction();
 }}}

--
Ticket URL: <http://devel.rtems.org/ticket/2438>
RTEMS Project <http://www.rtems.org/>
RTEMS Project