[RTEMS Project] #3007: ARM caching issues
RTEMS trac
trac at rtems.org
Tue May 9 07:58:16 UTC 2017
#3007: ARM caching issues
-------------------------------+------------------------------
Reporter: munster | Owner: joel.sherrill@…
Type: defect | Status: new
Priority: normal | Milestone: 4.12
Component: bsps | Version: 4.12
Severity: normal | Resolution:
Keywords: ARM,cache,L2C 310 |
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Comment (by Sebastian Huber):
Replying to [comment:5 munster]:
> Replying to [comment:4 Sebastian Huber]:
> > Please don't change the function signatures. Please generate one patch
for each issue.
> I have attached separate patches for these two issues.
Could you please format the patches via "git format-patch":
https://devel.rtems.org/wiki/Developer/Contributing
Please help to improve the wiki and website if something is unclear or
hard to find.
>
> > Its up to the user to ensure that a cache line invalidation is safe.
The cache manager should not take care of this.
> Generally you are right. However, the user may not be aware of this
particular problem.
The we should fix this issue with better documentation. In
https://git.rtems.org/rtems/tree/cpukit/rtems/include/rtems/rtems/cache.h#n111
we have
{{{
/**
* @brief Invalidates multiple data cache lines.
*
* The cache lines covering the area are marked as invalid. A later read
* access in the area will load the data from memory.
*
* In case the area is not aligned on cache line boundaries, then this
* operation may destroy unrelated data.
*
* @param[in] addr The start address of the area to invalidate.
* @param[in] size The size in bytes of the area to invalidate.
*/
void rtems_cache_invalidate_multiple_data_lines(
const void *addr,
size_t size
);
}}}
The cache manager documentation probably needs to move into the user
manual. Maybe some examples help to show what can go wrong.
--
Ticket URL: <http://devel.rtems.org/ticket/3007#comment:6>
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