[RTEMS Project] #2004: sparc64: problem using softint and timer together

[RTEMS trac]

#2004: sparc64: problem using softint and timer together
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 Reporter:  Gedare  |       Owner:  Gedare
     Type:  defect  |      Status:  accepted
 Priority:  normal  |   Milestone:  Indefinite
Component:  bsps    |     Version:  4.11
 Severity:  normal  |  Resolution:
 Keywords:          |  Blocked By:
 Blocking:          |
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Changes (by Gedare):

 * milestone:  4.11.3 => Indefinite


Old description:

> sparc64 hardware shares an interrupt level (14) between tick comparison
> and software-raised  interrupts. current bsps do not handle the situation
> of both interrupt sources simultaneously, so software interrupts cannot
> be used when the timer also is used.  What happens is the interrupt level
> (PIL) does not get set/reset properly and interrupts are missed.
>
> The attached patch is a work-around that hacks the clock isr, but I need
> to look more closely at the generic ISR handling code to see if the bug
> is due to interactions between PIL assignment, interrupt enable/disable,
> and scheduling.

New description:

 sparc64 hardware shares an interrupt level (14) between tick comparison
 and software-raised  interrupts. current bsps do not handle the situation
 of both interrupt sources simultaneously, so software interrupts cannot be
 used when the timer also is used.  What happens is the interrupt level
 (PIL) does not get set/reset properly and interrupts are missed.

 The attached patch is a work-around that hacks the clock isr, but I need
 to look more closely at the generic ISR handling code to see if the bug is
 due to interactions between PIL assignment, interrupt enable/disable, and
 scheduling.

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Ticket URL: <http://devel.rtems.org/ticket/2004#comment:9>
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