[RTEMS Project] #3433: Add SMP support for RISC-V

[RTEMS trac]

#3433: Add SMP support for RISC-V
-----------------------------+-------------------------------
 Reporter:  Sebastian Huber  |       Owner:  Sebastian Huber
     Type:  project          |      Status:  accepted
 Priority:  normal           |   Milestone:  6.1
Component:  arch/riscv       |     Version:
 Severity:  normal           |  Resolution:
 Keywords:                   |  Blocked By:  3452, 3453, 3459
 Blocking:                   |
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Comment (by Sebastian Huber <sebastian.huber@…>):

 In [changeset:"3a646426aa421ab3e229ec483d8b29f2f56c29ac/rtems"
 3a646426/rtems]:
 {{{
 #!CommitTicketReference repository="rtems"
 revision="3a646426aa421ab3e229ec483d8b29f2f56c29ac"
 score: Add _CPU_Instruction_illegal()

 On some architectures/simulators it is difficult to provoke an
 exception with misaligned or illegal data loads.  Use an illegal
 instruction instead.

 Update #3433.
 }}}

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Ticket URL: <http://devel.rtems.org/ticket/3433#comment:55>
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