[RTEMS Project] #3433: Add SMP support for RISC-V

[RTEMS trac]

#3433: Add SMP support for RISC-V
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 Reporter:  Sebastian Huber  |       Owner:  Sebastian Huber
     Type:  project          |      Status:  accepted
 Priority:  normal           |   Milestone:  6.1
Component:  arch/riscv       |     Version:
 Severity:  normal           |  Resolution:
 Keywords:                   |  Blocked By:  3452, 3453, 3459
 Blocking:                   |
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Comment (by Sebastian Huber <sebastian.huber@…>):

 In [changeset:"b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684/rtems"
 b706b4a/rtems]:
 {{{
 #!CommitTicketReference repository="rtems"
 revision="b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684"
 riscv: Remove mstatus from thread context

 The mstatus register contains no thread-specific state which must be
 saved/restored during a context switch.  Machine interrupts (MIE) must
 be enabled during a context switch.

 Create separate CPU_Interrupt_frame structure.

 Update #3433.
 }}}

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Ticket URL: <http://devel.rtems.org/ticket/3433#comment:33>
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