[RTEMS Project] #3337: RISC-V Port in Supervisor Mode

[RTEMS trac]

#3337: RISC-V Port in Supervisor Mode
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  Reporter:  Hesham Almatary  |      Owner:  (none)
      Type:  project          |     Status:  new
  Priority:  normal           |  Milestone:  Indefinite
 Component:  arch/riscv32     |    Version:
  Severity:  normal           |   Keywords:
Blocked By:                   |   Blocking:
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 Enable the RISC-V Port to run in RISC-V's Supervisor Mode (S-Mode).

 **Status**:

 Uninitiated.

 **Introduction**:

 RISC-V port was merged in October 2017. However, it only runs in Machine
 Mode (M-Mode) which only has base-and-bound protection, but not
 implemented in RTEMS. RISC-V has a Supervisor Mode (S-Mode), which has an
 MMU and paging-based protection.

 **Goal**:

 The goal is to be able to "optionally" run RISC-V port in S-Mode.

 **Requirements**:

     Knowledge of assembly, C Programming language.
     Knowledge of RISC-V architecture.
     Study the implementation of riscv-pk project (RTEMS will rely on it).
     Debugging experience especially at low-level/system levels.


 **Resources**:

     Current RTEMS developers.
     RISC-V's user-spec and priv-1.10 manuals.


 **Getting started as a GSoC student on this Project**

 If you are interested in working on this project as a GSoC project, there
 are a few basics you should do.

 You'll need to build the simulators (hint: Spike and/or QEMU), from riscv-
 tools/priv-1.10.

 **Build the rtems*-riscv toolchain from rtems-source-builder**

 **Build & run the BSP**

 Build & run the current RISC-V BSP (e.g. using the test set) and run it on
 Spike and/or QEMU.


 To show that you're up to speed with rebuilding RTEMS, make a change.
 Showing the result must be part of your proposal.



 **The official requirement is a ​Hello World project.**


 **References**
     [https://devel.rtems.org/wiki/GSoC/GettingStarted Hello World Project]
     [https://riscv.org/specifications/ RISC-V Specifications (priv-1.10)]
     [https://github.com/riscv/riscv-
 pk/tree/66701f82f88d08d3700d8b0bc5d5306abfd0044f RISC-V's Proxy Kernel]
     [https://github.com/riscv/riscv-tools/tree/priv-1.10 RISC-V's 1.10
 tools]

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Ticket URL: <http://devel.rtems.org/ticket/3337>
RTEMS Project <http://www.rtems.org/>
RTEMS Project