[RTEMS Project] #3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA

[RTEMS trac]

#3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA
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 Reporter:  pragnesh                       |       Owner:  (none)
     Type:  task                           |      Status:  new
 Priority:  normal                         |   Milestone:  5.1
Component:  arch/riscv                     |     Version:  5
 Severity:  normal                         |  Resolution:
 Keywords:  #RISCV, #FREEDOME310, #ARTYA7  |  Blocked By:
 Blocking:                                 |
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Comment (by Pragnesh Patel <pragnesh.patel@…>):

 In [changeset:"a7f5e42cc5234f239a01b8f69847ebb018710948/rtems"
 a7f5e42c/rtems]:
 {{{
 #!CommitTicketReference repository="rtems"
 revision="a7f5e42cc5234f239a01b8f69847ebb018710948"
 riscv: add freedom E310 Arty A7 bsp

 Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
 Update #3785.

 Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
 }}}

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Ticket URL: <http://devel.rtems.org/ticket/3785#comment:4>
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