[RTEMS Project] #4013: Using the size of an object to deduce the alignment is broken on some architectures

[RTEMS trac]

#4013: Using the size of an object to deduce the alignment is broken on some
architectures
-----------------------------+------------------------------
 Reporter:  Sebastian Huber  |       Owner:  Sebastian Huber
     Type:  defect           |      Status:  assigned
 Priority:  normal           |   Milestone:  5.2
Component:  score            |     Version:  5
 Severity:  normal           |  Resolution:
 Keywords:                   |  Blocked By:
 Blocking:                   |
-----------------------------+------------------------------

Comment (by Chris Johns):

 Replying to [comment:6 Sebastian Huber]:
 > This ticket is not about the stack pointer. It is about the alignment of
 objects and in particular partitions. When the compiler places something
 like this on 2-byte alignment
 > {{{
 > typedef struct {
 >   uint64_t data [16];
 > } area;
 >
 > #if CONFIGURE_MAXIMUM_PARTITIONS > 0
 >   static area partition_areas [CONFIGURE_MAXIMUM_PARTITIONS];
 > #endif
 > }}}
 > with -O2, then the performance cannot be that bad on this architecture.
 >
 > The user has always the option to fine tune this. Why should RTEMS
 enforce artificial alignment requirements?

 The stack pointer is provided as an example of the extreme end of the
 issue and while what you show is simpler and the overheads might not be as
 apparent they are present. Also please remember the m68k does not have a
 pipeline or a smart bus interface that can join accesses in a pipeline
 into a single larger access that other architectures can.

 Consider a standard prologue for a function on a m68k. It will be
 something like:
 {{{
 movem.l a0-a7,sp-
 }}}
 If the m68k has a 32bit bus and the SP is mis-aligned it will silently use
 a bus cycle for each half of the 32bit value written or two bus cycles for
 each 32bit word. If the SP was aligned on a long-word boundary half the
 number of cycles would be need. The m68k/Coldfire designers designed the
 device assuming the SP would be long word aligned even through it can
 support being misaligned. We need to capture and enforce this or we
 degrade the performance of the system.

 The issue is way the address bus is set out, there is no `A0` or `A1`,
 they are data strobes to gate the part of the 32 bit data that is active
 for the access.

--
Ticket URL: <http://devel.rtems.org/ticket/4013#comment:9>
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