[RTEMS Project] #4749: Clock Driver Validation

[RTEMS trac]

#4749: Clock Driver Validation
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 Reporter:  Matt Joyce               |       Owner:  Sebastian Huber
     Type:  enhancement              |      Status:  assigned
 Priority:  normal                   |   Milestone:
Component:  test                     |     Version:  6
 Severity:  normal                   |  Resolution:
 Keywords:  clock driver, testsuite  |  Blocked By:
 Blocking:                           |
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Comment (by Chris Johns):

 What about suitable hardware IO on the board to receive the PPS signal and
 generate an interrupt? I assume it is a TTL level signal we are
 discussing?

 How will the test be selected for each BSP in the build to avoid erroneous
 error reports for BSPs that do not have support?

 What is the tolerance of the detection per BSP given the variability of
 the PPS latency, PPM of clock sources, temperature and timer hardware each
 BSP may have?

 If I have a high clock frequency as an input signal to the timer and a
 large divider what resolution and error range be used to pass or fail the
 test?

 I think this is an interesting and challenging problem to solve. I am
 interested to see how it can detect the off by one timer reload error you
 highlighted. For an A9 with a CPU x1 clock of 750MHz and a peripheral
 clock of 350MHz feeding the timer the internal count for a 1msec interrupt
 is 350,000 (I think). An error in the count of one is a small amount of
 time.

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Ticket URL: <http://devel.rtems.org/ticket/4749#comment:3>
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