[RTEMS Project] #4735: riscv start.S for a singlecore on a multicore device

[RTEMS trac]

#4735: riscv start.S for a singlecore on a multicore device
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  Reporter:  Lucian-Raul Silistru  |      Owner:  (none)
      Type:  enhancement           |     Status:  new
  Priority:  normal                |  Milestone:
 Component:  arch/riscv            |    Version:  5
  Severity:  normal                |   Keywords:
Blocked By:                        |   Blocking:
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 We have run into a use-case where we are running non-SMP RTEMS on a riscv
 device with multiple harts that are pulled out of reset at the same time.
 All cores run the same code as the boot hartid - with predictable results
 (same int stack, same bss, all call boot_card).

 Is there a plan/desire to support blocking any non-boot harts in a WFI
 loop, even in non-SMP? Or an infinite loop or a similar loop to SMP (+ a
 WFI)?

 I saw singlecore SMP (with multicore device) parks any unused cores in
 Idle.

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Ticket URL: <http://devel.rtems.org/ticket/4735>
RTEMS Project <http://www.rtems.org/>
RTEMS Project