[RTEMS Project] #4735: riscv start.S for a single core on a multicore device

[RTEMS trac]

#4735: riscv start.S for a single core on a multicore device
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 Reporter:  Lucian-Raul Silistru  |       Owner:  Needs Funding
     Type:  enhancement           |      Status:  assigned
 Priority:  normal                |   Milestone:  Indefinite
Component:  arch/riscv            |     Version:  5
 Severity:  normal                |  Resolution:
 Keywords:                        |  Blocked By:
 Blocking:                        |
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Changes (by Sebastian Huber):

 * owner:  (none) => Needs Funding
 * status:  new => assigned
 * milestone:   => Indefinite


Comment:

 This should be easy to support with a BSP option. For example,
 RISCV_START_BOOT_HARTID. If this option is defined and RTEMS_SMP is not
 defined, then start.S loops if the hardid is not equal to the value of
 RISCV_START_BOOT_HARTID.

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Ticket URL: <http://devel.rtems.org/ticket/4735#comment:2>
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