[RTEMS Project] #4771: Versal UART issues

RTEMS trac trac at rtems.org
Thu Feb 9 02:27:13 UTC 2023

#4771: Versal UART issues
 Reporter:  Chris Johns   |       Owner:  Chris Johns
     Type:  defect        |      Status:  assigned
 Priority:  normal        |   Milestone:  6.1
Component:  arch/aarch64  |     Version:  6
 Severity:  normal        |  Resolution:
 Keywords:                |  Blocked By:
 Blocking:                |

Comment (by Chris Johns):

 The UART IP is based on the standard ARM IP however Xilinx have finally
 reported to me the interrupts are not the same as the ARM IP. There is
 weird issue around needing to prime the FIFO to half plus one to generate
 the first TX interrupt.

 Xilinx has confirmed this will not change across the range of ACAP

 The main issue this raises is using the UART for a specialized protocol
 and not a terminal where sending a number of carriage returns is harmless.

Ticket URL: <http://devel.rtems.org/ticket/4771#comment:1>
RTEMS Project <http://www.rtems.org/>
RTEMS Project

More information about the bugs mailing list