[RTEMS Project] #4923: FPU context init/switch not working well on more than 2 tasks on Cortex-Mx/ARMv7-M platform

[RTEMS trac]

#4923: FPU context init/switch not working well on more than 2 tasks on Cortex-
Mx/ARMv7-M platform
----------------------+---------------------
 Reporter:  kgardas   |       Owner:  (none)
     Type:  defect    |      Status:  new
 Priority:  normal    |   Milestone:
Component:  arch/arm  |     Version:
 Severity:  major     |  Resolution:
 Keywords:            |  Blocked By:
 Blocking:            |
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Comment (by kgardas):

 Here is the output of spcontext01 on nucleo-h743zi:
 {{{
 *** BEGIN OF TEST SPCONTEXT 1 ***
 *** TEST VERSION: 6.0.0.6264b14804bbe21f13d4691160b45e208286abaa
 *** TEST STATE: EXPECTED_PASS
 *** TEST BUILD:
 *** TEST TOOLS: 12.2.1 20230224 (RTEMS 6, RSB
 7153c2f1dcfb83b154b976298699c26e793a33dd, Newlib 17ac400)
 Test configuration N N N... done
 Test configuration N N F... done
 Test configuration N F N... done
 Test configuration N F F... done
 Test configuration F N N... done
 Test configuration F N F... done
 Test configuration F F N... done
 Test configuration F F F... done

 *** END OF TEST SPCONTEXT 1 ***


 [ RTEMS shutdown ]
 RTEMS version: 6.0.0.6264b14804bbe21f13d4691160b45e208286abaa
 RTEMS tools: 12.2.1 20230224 (RTEMS 6, RSB
 7153c2f1dcfb83b154b976298699c26e793a33dd, Newlib 17ac400)
 executing thread ID: 0x0a010001
 executing thread name: UI1
 }}}

 Let me know if there is anything I should test here. I have some spare
 time at my disposal, but I'd need to be kicked into the right direction.
 Currently studding Cortex-M lazy stacking and context switching and RTEMS
 book is ordered as a backup and will be here probably next week. I'll also
 provide few registers dumps for your information...

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Ticket URL: <http://devel.rtems.org/ticket/4923#comment:3>
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