RTEMS | Add Intel NIOS V BSP support to the RISC-V architecture (#5101)

[Kevin Kirspel (@kirspelk)]

Kevin Kirspel created an issue: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5101



## Summary
The Intel NIOS V is synthesizable verilog model of a processor that implements the RISC-V architecture in Intel FPGA products.  The verilog model comes in three variants: NIOS V/c, NIOS V/m, and NIOS V/g. This BSP supports variants V/m and V/g. The V/g variant is supported with or without an FPU.  The V/c variant is not supported due to it's lack of an interrupt controller.

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5101
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