Documentation | Draft: Add Intel NIOS V BSP to RISC-V section of user's manual (!39)

[Kevin Kirspel (@kirspelk)]

Kevin Kirspel commented on a discussion on user/bsps/bsps-riscv.rst: https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/39#note_110899

 >  
 >  This RISC-V BSP supports chips using the
 >  `GRLIB <https://www.gaisler.com/products/grlib/grlib.pdf>`_.
 > +
 > +NIOS V
 > +======
 > +
 > +This BSP supports the `NIOS V <https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/processors-peripherals/niosv.html>`_
 > +systems from Intel. The NIOS V is a synthesizable verilog model of a processor

Capitalized Verilog in latest commit.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/39#note_110899
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