RTEMS | Adding a new NIOS V BSP to the RISC-V architecture (!174)

[Kevin Kirspel (@kirspelk)]

Kevin Kirspel commented on a discussion on bsps/riscv/niosv/supporting.zip: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/174#note_110989


This BSP is just an example NIOS V BSP which uses a Intel Cyclone 10 LP Evaluation Board with a FPGA configuration that is described in the README.md. The supporting.zip file contains files that are referenced in the README.md. The README.md is intended to be used as a guide for creating a real BSP based on a real NIOS V based FPGA system. It contains the steps necessary to start with a Quartus Prime project to building a RTEMS BSP. I could move the README.md contents into the user's manual but it would contain all the Quartus instructions that are unrelated to RTEMS. That is why I just left it in the BSP itself.  Even if I move it into the user's manual, the supporting.zip file would still need to be accessible.

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/174#note_110989
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