RTEMS | Add RISCV libdl support (!312)

[Pavel Pisa (@ppisa)]

Pavel Pisa commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/312#note_115166


When I decode `mcause` it reports 4 Load address misaligned and when I analyze the initial case then it is `lw      a4,0(s0)` where `s0` is `0x00000010001b97e6`. So this matches. It seems that misaligned accesses are disabled on CPU level. But GCC and ISA expects that they are enabled. So RTEMS startup code should enable them. I try to find how they are enabled and supported on PolarFire.

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/312#note_115166
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