RTEMS | aarch64_mmu_enable end up without dsb and isb cause failure (#5237)

[geng zhu (@zhugengyu2023)]

geng zhu created an issue: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5237



- As refer to Bare-metal Boot Code for ARMv8-A Processors
Application Note 527 (https://developer.arm.com/documentation/dai0527/latest/)，after enable mmu, DSB/ISB should exists for coherency, but the aarch64_mmu_enable now not have, which cause failure when clear bss in my board

![image](/uploads/70d386af31a81d4cb09f72e6c7d44624/image.png){width=819 height=557}

```
BSP_START_TEXT_SECTION static inline void
aarch64_mmu_enable( const aarch64_mmu_control *control )
{
  uint64_t sctlr;

  /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */

  /* Flush and invalidate cache */
  rtems_cache_flush_entire_data();

  _AArch64_Write_ttbr0_el1( (uintptr_t) control->ttb );
  _AARCH64_Instruction_synchronization_barrier();

  /* Enable MMU and cache */
  sctlr = _AArch64_Read_sctlr_el1();
  sctlr |= AARCH64_SCTLR_EL1_I | AARCH64_SCTLR_EL1_C | AARCH64_SCTLR_EL1_M;
  _AArch64_Write_sctlr_el1( sctlr );

  /* Sync here */
  _AARCH64_Data_synchronization_barrier();
  _AARCH64_Instruction_synchronization_barrier();
}
```

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5237
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