RTEMS | aarch64: The FPSCR (FPSR/FPCR) and FPEXC registers do not have thread storage (#5214)

[Kinsey Moore (@opticron)]

Kinsey Moore commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119875


Do you agree with these points?:
* FPSR upon entering the function is effectively random as per `may have any value on entry to a subroutine`.
* A function wants to know what FP exceptions its code triggers.
* To know this, all FP exception bits must be unset.
* According to your interpretation, this would require saving FPSR for later restoration.
* According to your interpretation, this would make FPSR a callee-saved register.
* According to your interpretation, this would make FPSR the only callee-saved register to be defined as such without explicitly labeling it so in the AArch64 PCS.

My interpretation of the quoted block is that the FPSR is cumulative across instructions until a function is called. That function is allowed to do whatever it wants with the FPSR including clear it because that's what any function that utilizes FP instructions will have to do to detect errors. Since FPSR is not explicitly labeled as callee-saved, the function has no need to restore its original value.

A register is either callee-saved or caller-saved. If the callee is allowed to return it with modifications (which your interpretation allows for), that makes it caller-saved.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119875
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