RTEMS | aarch64: The FPSCR (FPSR/FPCR) and FPEXC registers do not have thread storage (#5214)

Fri Feb 14 01:39:32 UTC 2025

Kinsey Moore commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119884

The fact that a context switch is occurring is irrelevant. Any function call that uses FP instructions could invalidate the FPSR from the calling function's perspective. If you set specific bits in the FPSR and then call sqrt(-1), is the pre-call FPSR preserved in the manner that you're suggesting?

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119884
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