RTEMS | aarch64: The FPSCR (FPSR/FPCR) and FPEXC registers do not have thread storage (#5214)

[Preston Faiks (@pfaiks)]

Preston Faiks commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_120103


Thread-level (rather than system-level) is done by multiple other rtems BSPs. For example [Sparc](https://gitlab.rtems.org/rtems/rtos/rtems/-/blob/main/cpukit/score/cpu/sparc/cpu_asm.S?ref_type=heads#L738) and [PowerPC](https://gitlab.rtems.org/rtems/rtos/rtems/-/blob/main/bsps/powerpc/shared/cpu_asm.S?ref_type=heads#L175). So this really isn't a new feature.

I think the usefulness of this is unquestionably better than having applications save/restore state before every single function which might invoke a context switch. Many systems have a code base that is impractical to modify to such a large extent.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_120103
You're receiving this email because of your account on gitlab.rtems.org.


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/bugs/attachments/20250220/22e02ec9/attachment.htm>