RTEMS | RISC-V SMP start reads 64bits from a 32bit symbol (#5251)

[Lucian Silistru (@lsilistr)]

Lucian Silistru created an issue: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5251



## Summary
`_SMP_Processor_configured_maximum` is defined as a uint32_t here:
https://gitlab.rtems.org/rtems/rtos/rtems/-/blob/main/cpukit/include/rtems/confdefs/percpu.h#L71
In riscv start.S it is read by LREG macro that on rv64 is a ld. It will also read the next 32 bits over in the MS half of the doubleword:
https://gitlab.rtems.org/rtems/rtos/rtems/-/blob/main/bsps/riscv/shared/start/start.S?ref_type=heads#L77

I think https://gitlab.rtems.org/rtems/rtos/rtems/-/blob/main/bsps/aarch64/shared/start/start.S#L241 has the same issue, but it's been a while since I ran an aarch64, ldr X<N> should be 64 bit load.

## Steps to reproduce
Err, just happened to have != 0 in the 32 bits above _SMP_Processor_configured_maximum address, and the second core went crazy.

### Pre-set options

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5251
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