RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Kinsey Moore (@opticron)]

Kinsey Moore commented on a discussion on bsps/riscv/esp32/start/bspstart.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147701

 > +  uint32_t timg_wdtconfig0 = TIMG_READ(TIMG_WDTCONFIG0_REG);
 > +  TIMG_WRITE(TIMG_WDTCONFIG0_REG, timg_wdtconfig0 & TIMG_WDTCONFIG0_EN);
 > +
 > +  bsp_interrupt_initialize();
 > +}
 > +
 > +/* src is the offset in flash */
 > +BSP_START_TEXT_SECTION static inline void
 > +copy_from_flash_offset(void *dest, const void *src, size_t n)
 > +{
 > +  /* The RAM load sections are offset from 0x0, offset from mapped flash base */
 > +  uintptr_t flash_base = 0x3c000000;
 > +
 > +  uintptr_t flash_address = ((uintptr_t)src);
 > +  flash_address += flash_base;
 > +  memcpy(dest, (void *)flash_address, n);

Yes, these are unrelated memory areas. This is copying from mapped flash to SRAM.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147701
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