RTEMS | ESP-32 C5 and C6 (#5527)

Wed Apr 1 13:41:29 UTC 2026

Kinsey Moore commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527#note_147782

There is a comment just above the `#define` that explains why it's 63 instead of 62.

Those interrupts being used for software interrupts are defined as interrupts from other cores in the datasheet. They can be used by any core to send interrupts to any other core, but don't have hard-set usages as they are just inter-processor interrupts.

Yes, I had to find the ROM function addresses elsewhere. I did not see them at all in the datasheet. There should be a full breakdown in the IDF SDK for each chip.

You would define your own chip_definitions file for other chips. `c3/chip_definitions.h` should remain unmodified.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527#note_147782
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