RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Kinsey Moore (@opticron)]

Kinsey Moore commented on a discussion on bsps/riscv/esp32/include/bsp/irq.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147786

 > + * SUCH DAMAGE.
 > + */
 > +
 > +#ifndef LIBBSP_ESP32_BSP_IRQ_H
 > +#define LIBBSP_ESP32_BSP_IRQ_H
 > +
 > +#include <rtems/score/basedefs.h>
 > +#include <bspopts.h>
 > +#define JOIN_PATHS(path1, path2) RTEMS_XSTRING(path1/path2)
 > +
 > +typedef int (*uart_tx_one_char_t)(uint8_t c);
 > +typedef void (*uart_tx_flush_t)(uint8_t uart_no);
 > +typedef unsigned char (*uart_rx_one_char_t)(unsigned char *char_in);
 > +typedef void (*gpio_output_set_t)(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
 > +
 > +#include JOIN_PATHS(ESPRESSIF_CHIP_VARIANT, chip_definitions.h)

I have moved the magic from the header file to the spec option definition.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147786
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