RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1160
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160

* 2e9e44a0...215b3c9f - 2 commits from branch `main`

* db85fedb - riscv: Add support for Espressif Direct Boot
* 9a4f2904 - riscv: Add optional section copy callback
* 1d98a007 - spec/bsps/riscv: Allow start section load address
* 9520d150 - spec/riscv: Allow BSS to be specified independent of DATA
* ae1dd8de - riscv: Add support for vectored interrupt controllers
* 3ff994ce - cpukit/riscv: Make use of MDT conditional on Zicsr
* b5ebe6bf - riscv: Add basic ESP32-C3 BSP

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160
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