RTEMS | riscv: Add ESP32-C6 chip definitions (!1186)

[Kinsey Moore (@opticron)]

Kinsey Moore started a new discussion on bsps/riscv/esp32/include/c6/chip_definitions.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148272

 > +#define GDMA_IN_CH2_INTR            68
 > +#define GDMA_OUT_CH0_INTR           69
 > +#define GDMA_OUT_CH1_INTR           70
 > +#define GDMA_OUT_CH2_INTR           71
 > +#define GPSPI2_INTR                 72
 > +#define AES_INTR                    73
 > +#define SHA_INTR                    74
 > +#define RSA_INTR                    75
 > +#define ECC_INTR                    76
 > +
 > +/*
 > + * Not sure these 2 below
 > + * Would it be System Register (there are 2) - LP_PERI_TIMEOUT_INTR (19) or CPU_PERI_TIMEOUT_INTR (29)?
 > + */
 > +#define RISCV_INTERRUPT_VECTOR_SOFTWARE LP_PERI_TIMEOUT_INTR      //  System Registers - 19
 > +#define RISCV_INTERRUPT_VECTOR_TIMER    SYSTIMER_TARGET0_INTR     //  System Timer(SYSTIMER) - 57

This is fine for initial porting. It may be worthwhile to transition to the CLINT timer interrupt source.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1186#note_148272
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